microchip/sparx5/sparx5_main_regs.h

82 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\
83 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
84 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\
85 	FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
88 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\
89 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
90 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\
91 	FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
99 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\
100 	FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
101 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\
102 	FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
110 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\
111 	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
112 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\
113 	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
116 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\
117 	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
118 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\
119 	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
122 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\
123 	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x)
124 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\
125 	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x)
128 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\
129 	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
130 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\
131 	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
134 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\
135 	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
136 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\
137 	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
140 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\
141 	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
142 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\
143 	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
163 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\
164 	FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
165 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\
166 	FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
186 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\
187 	FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
188 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\
189 	FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
209 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\
210 	FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
211 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\
212 	FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
220 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\
221 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
222 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\
223 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
226 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\
227 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
228 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\
229 	FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
232 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\
233 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
234 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\
235 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
243 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\
244 	FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
245 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\
246 	FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
250 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\
251 	spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x)
252 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\
253 	spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x)
262 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\
263 	spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
264 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\
265 	spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
268 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\
269 	FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
270 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\
271 	FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
274 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\
275 	FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
276 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\
277 	FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
280 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\
281 	FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
282 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\
283 	FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
291 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\
292 	FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
293 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\
294 	FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
297 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\
298 	FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
299 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\
300 	FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
304 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\
305 	spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
306 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\
307 	spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
310 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\
311 	FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
312 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\
313 	FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
322 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\
323 	spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x)
324 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\
325 	spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x)
328 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\
329 	FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
330 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\
331 	FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
339 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\
340 	FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
341 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\
342 	FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
345 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\
346 	FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
347 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\
348 	FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
366 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\
367 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
368 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\
369 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
372 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\
373 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
374 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\
375 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
378 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\
379 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
380 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\
381 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
384 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\
385 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
386 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\
387 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
390 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\
391 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
392 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\
393 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
396 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\
397 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
398 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\
399 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
402 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\
403 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
404 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\
405 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
408 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\
409 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
410 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\
411 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
414 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\
415 	FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
416 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\
417 	FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
435 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\
436 	FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
437 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\
438 	FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
441 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\
442 	FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
443 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\
444 	FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
472 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\
473 	FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
474 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\
475 	FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
478 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\
479 	FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
480 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\
481 	FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
484 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\
485 	FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x)
486 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\
487 	FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x)
490 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\
491 	FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
492 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\
493 	FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
496 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\
497 	FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
498 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\
499 	FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
513 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\
514 	spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x)
515 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\
516 	spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x)
524 #define ANA_AC_STAT_RESET_RESET_SET(x)\
525 	FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
526 #define ANA_AC_STAT_RESET_RESET_GET(x)\
527 	FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
535 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\
536 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
537 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\
538 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
541 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\
542 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
543 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\
544 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
547 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\
548 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
549 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\
550 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
563 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\
564 	FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
565 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\
566 	FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
574 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\
575 	FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
576 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\
577 	FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
585 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\
586 	FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
587 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\
588 	FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
596 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\
597 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
598 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\
599 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
602 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\
603 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
604 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\
605 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
608 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\
609 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
610 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\
611 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
614 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\
615 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
616 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\
617 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
620 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\
621 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
622 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\
623 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
626 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\
627 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
628 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\
629 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
632 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\
633 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
634 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\
635 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
638 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\
639 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
640 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\
641 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
644 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\
645 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
646 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\
647 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
650 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\
651 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
652 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\
653 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
656 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\
657 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
658 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\
659 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
662 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\
663 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
664 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\
665 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
668 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\
669 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
670 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\
671 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
674 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\
675 	FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
676 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\
677 	FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
685 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\
686 	FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
687 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\
688 	FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
691 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\
692 	FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
693 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\
694 	FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
697 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\
698 	FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
699 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\
700 	FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
703 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\
704 	FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
705 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\
706 	FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
709 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\
710 	FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
711 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\
712 	FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
720 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\
721 	FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
722 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\
723 	FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
726 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\
727 	FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
728 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\
729 	FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
737 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\
738 	FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
739 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\
740 	FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
743 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\
744 	FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
745 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\
746 	FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
749 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\
750 	FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
751 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\
752 	FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
760 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\
761 	FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
762 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\
763 	FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
771 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\
772 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
773 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\
774 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
777 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\
778 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
779 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\
780 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
783 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\
784 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
785 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\
786 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
789 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\
790 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
791 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\
792 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
795 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\
796 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
797 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\
798 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
801 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\
802 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
803 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\
804 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
807 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\
808 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
809 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\
810 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
813 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\
814 	FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
815 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\
816 	FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
834 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\
835 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
836 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\
837 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
840 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\
841 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
842 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\
843 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
846 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\
847 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
848 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\
849 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
852 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\
853 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
854 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\
855 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
858 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\
859 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
860 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\
861 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
864 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\
865 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
866 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\
867 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
870 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\
871 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
872 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\
873 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
876 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\
877 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
878 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\
879 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
882 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\
883 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
884 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\
885 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
888 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\
889 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
890 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\
891 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
894 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\
895 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
896 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\
897 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
900 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\
901 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
902 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\
903 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
906 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\
907 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
908 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\
909 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
912 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\
913 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
914 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\
915 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
918 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\
919 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
920 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\
921 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
924 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\
925 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
926 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\
927 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
930 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\
931 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
932 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\
933 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
936 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\
937 	FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
938 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\
939 	FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
947 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\
948 	FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
949 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\
950 	FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
958 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
959 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
960 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
961 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
964 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
965 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
966 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
967 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
970 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\
971 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
972 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\
973 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
976 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
977 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
978 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
979 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
987 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
988 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
989 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
990 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
993 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
994 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
995 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
996 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
999 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\
1000 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
1001 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\
1002 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
1005 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
1006 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
1007 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
1008 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
1017 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\
1018 	spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x)
1019 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\
1020 	spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x)
1028 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\
1029 	FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
1030 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\
1031 	FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
1039 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\
1040 	FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
1041 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\
1042 	FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
1045 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\
1046 	FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
1047 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\
1048 	FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
1057 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\
1058 	spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
1059 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\
1060 	spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
1068 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\
1069 	FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
1070 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\
1071 	FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
1079 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\
1080 	FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
1081 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\
1082 	FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
1085 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\
1086 	FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
1087 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\
1088 	FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
1092 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\
1093 	spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
1094 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\
1095 	spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
1103 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\
1104 	FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
1105 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\
1106 	FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
1114 #define ANA_AC_SDLB_THRES_THRES_SET(x)\
1115 	FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x)
1116 #define ANA_AC_SDLB_THRES_THRES_GET(x)\
1117 	FIELD_GET(ANA_AC_SDLB_THRES_THRES, x)
1120 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\
1121 	FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x)
1122 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\
1123 	FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x)
1132 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\
1133 	spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
1134 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\
1135 	spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
1139 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\
1140 	spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
1141 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\
1142 	spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
1150 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\
1151 	FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1152 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\
1153 	FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1156 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\
1157 	FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1158 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\
1159 	FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1162 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\
1163 	FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1164 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\
1165 	FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1174 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\
1175 	spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1176 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\
1177 	spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1185 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\
1186 	FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1187 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\
1188 	FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1191 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\
1192 	FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1193 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\
1194 	FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1197 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\
1198 	FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1199 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\
1200 	FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1208 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\
1209 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1210 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\
1211 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1214 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\
1215 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1216 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\
1217 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1220 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\
1221 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1222 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\
1223 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1226 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\
1227 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1228 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\
1229 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1232 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\
1233 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1234 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\
1235 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1238 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\
1239 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1240 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\
1241 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1244 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\
1245 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1246 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\
1247 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1250 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\
1251 	FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1252 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\
1253 	FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1261 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\
1262 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1263 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\
1264 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1267 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\
1268 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1269 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\
1270 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1273 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\
1274 	FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1275 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\
1276 	FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1284 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\
1285 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1286 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\
1287 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\
1291 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1292 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\
1293 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1296 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\
1297 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1298 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\
1299 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\
1303 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1304 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\
1305 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\
1309 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1310 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\
1311 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1314 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\
1315 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1316 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\
1317 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1320 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\
1321 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1322 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\
1323 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1326 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\
1327 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1328 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\
1329 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1332 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\
1333 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1334 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\
1335 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1338 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\
1339 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1340 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\
1341 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1344 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\
1345 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1346 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\
1347 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1355 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\
1356 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1357 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\
1358 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1361 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\
1362 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1363 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\
1364 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1372 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\
1373 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1374 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\
1375 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1378 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\
1379 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1380 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\
1381 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1384 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\
1385 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1386 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\
1387 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1390 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\
1391 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1392 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\
1393 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1396 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\
1397 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1398 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\
1399 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1402 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\
1403 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1404 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\
1405 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1408 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\
1409 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1410 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\
1411 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1414 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\
1415 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1416 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\
1417 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1420 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\
1421 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1422 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\
1423 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1426 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\
1427 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1428 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\
1429 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1432 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\
1433 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
1434 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\
1435 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
1443 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\
1444 	FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1445 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\
1446 	FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1454 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\
1455 	FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1456 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\
1457 	FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1460 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\
1461 	FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1462 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\
1463 	FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1471 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\
1472 	FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1473 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\
1474 	FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1477 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\
1478 	FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1479 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\
1480 	FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1483 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\
1484 	FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1485 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\
1486 	FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1489 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\
1490 	FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1491 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\
1492 	FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1495 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\
1496 	FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1497 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\
1498 	FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1501 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\
1502 	FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x)
1503 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\
1504 	FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x)
1507 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\
1508 	FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1509 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\
1510 	FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1513 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\
1514 	FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1515 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\
1516 	FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1519 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\
1520 	FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1521 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\
1522 	FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1525 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\
1526 	FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1527 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\
1528 	FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1531 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\
1532 	FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1533 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\
1534 	FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1537 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\
1538 	FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1539 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\
1540 	FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1553 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\
1554 	FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1555 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\
1556 	FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1559 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\
1560 	FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1561 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\
1562 	FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1570 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\
1571 	FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1572 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\
1573 	FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1576 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\
1577 	FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1578 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\
1579 	FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1582 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\
1583 	FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1584 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\
1585 	FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1588 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\
1589 	FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1590 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\
1591 	FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1594 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\
1595 	FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1596 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\
1597 	FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1600 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\
1601 	FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1602 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\
1603 	FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1606 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\
1607 	FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1608 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\
1609 	FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1617 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\
1618 	FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1619 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\
1620 	FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1628 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\
1629 	FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1630 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\
1631 	FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1634 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\
1635 	FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1636 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\
1637 	FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1640 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\
1641 	FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1642 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\
1643 	FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1646 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\
1647 	FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1648 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\
1649 	FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1652 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\
1653 	FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1654 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\
1655 	FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1663 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\
1664 	FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1665 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\
1666 	FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1674 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\
1675 	FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1676 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\
1677 	FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1680 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\
1681 	FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1682 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\
1683 	FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1686 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\
1687 	FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1688 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\
1689 	FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1692 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\
1693 	FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1694 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\
1695 	FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1698 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\
1699 	FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1700 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\
1701 	FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1704 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\
1705 	FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1706 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\
1707 	FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1710 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\
1711 	FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1712 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\
1713 	FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1716 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\
1717 	FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1718 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\
1719 	FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1722 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\
1723 	FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1724 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\
1725 	FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1728 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\
1729 	FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1730 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\
1731 	FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1734 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\
1735 	FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1736 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\
1737 	FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1740 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\
1741 	FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x)
1742 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\
1743 	FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x)
1763 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\
1764 	FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1765 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\
1766 	FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1775 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\
1776 	FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1777 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\
1778 	FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1787 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\
1788 	spx5_field_prep(ANA_L2_DLB_CFG_DLB_IDX, x)
1789 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\
1790 	spx5_field_get(ANA_L2_DLB_CFG_DLB_IDX, x)
1799 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\
1800 	spx5_field_prep(ANA_L2_TSN_CFG_TSN_SFID, x)
1801 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\
1802 	spx5_field_get(ANA_L2_TSN_CFG_TSN_SFID, x)
1810 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\
1811 	FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1812 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\
1813 	FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1821 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\
1822 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1823 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\
1824 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1827 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\
1828 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
1829 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\
1830 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
1833 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\
1834 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1835 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\
1836 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1839 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\
1840 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1841 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\
1842 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1845 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\
1846 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1847 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\
1848 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1851 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\
1852 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1853 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\
1854 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1857 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\
1858 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1859 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\
1860 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1863 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\
1864 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1865 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\
1866 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1869 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\
1870 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1871 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\
1872 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1892 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\
1893 	FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
1894 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\
1895 	FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
2348 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
2349 	FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2350 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
2351 	FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2359 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
2360 	FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2361 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
2362 	FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2370 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
2371 	FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2372 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
2373 	FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2381 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
2382 	FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2383 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
2384 	FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2392 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
2393 	FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2394 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
2395 	FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2403 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
2404 	FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2405 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
2406 	FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2414 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
2415 	FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2416 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
2417 	FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2425 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
2426 	FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2427 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
2428 	FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2441 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\
2442 	FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2443 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\
2444 	FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2452 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\
2453 	FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
2454 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\
2455 	FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
2458 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\
2459 	FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2460 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\
2461 	FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2464 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\
2465 	FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2466 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\
2467 	FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2470 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\
2471 	FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2472 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\
2473 	FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2476 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\
2477 	FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2478 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\
2479 	FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2482 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\
2483 	FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
2484 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\
2485 	FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
2488 #define ASM_PORT_CFG_PAD_ENA_SET(x)\
2489 	FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
2490 #define ASM_PORT_CFG_PAD_ENA_GET(x)\
2491 	FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
2494 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\
2495 	FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2496 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\
2497 	FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2500 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\
2501 	FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2502 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\
2503 	FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2506 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\
2507 	FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2508 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\
2509 	FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2512 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\
2513 	FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
2514 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\
2515 	FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
2523 #define ASM_RAM_INIT_RAM_INIT_SET(x)\
2524 	FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
2525 #define ASM_RAM_INIT_RAM_INIT_GET(x)\
2526 	FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
2529 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
2530 	FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2531 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
2532 	FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2540 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\
2541 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2542 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\
2543 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2546 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\
2547 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2548 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\
2549 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2552 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\
2553 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2554 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\
2555 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2558 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\
2559 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2560 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\
2561 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2564 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\
2565 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2566 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\
2567 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2570 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\
2571 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2572 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\
2573 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2582 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\
2583 	spx5_field_prep(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2584 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\
2585 	spx5_field_get(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2589 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\
2590 	spx5_field_prep(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2591 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\
2592 	spx5_field_get(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2596 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\
2597 	spx5_field_prep(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2598 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\
2599 	spx5_field_get(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2603 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\
2604 	spx5_field_prep(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2605 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\
2606 	spx5_field_get(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2610 #define CPU_PROC_CTRL_VINITHI_SET(x)\
2611 	spx5_field_prep(CPU_PROC_CTRL_VINITHI, x)
2612 #define CPU_PROC_CTRL_VINITHI_GET(x)\
2613 	spx5_field_get(CPU_PROC_CTRL_VINITHI, x)
2617 #define CPU_PROC_CTRL_CFGTE_SET(x)\
2618 	spx5_field_prep(CPU_PROC_CTRL_CFGTE, x)
2619 #define CPU_PROC_CTRL_CFGTE_GET(x)\
2620 	spx5_field_get(CPU_PROC_CTRL_CFGTE, x)
2624 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\
2625 	spx5_field_prep(CPU_PROC_CTRL_CP15S_DISABLE, x)
2626 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\
2627 	spx5_field_get(CPU_PROC_CTRL_CP15S_DISABLE, x)
2631 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\
2632 	spx5_field_prep(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2633 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\
2634 	spx5_field_get(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2638 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\
2639 	FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2640 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\
2641 	FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2645 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\
2646 	FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
2647 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\
2648 	FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
2652 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\
2653 	FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
2654 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\
2655 	FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
2659 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\
2660 	spx5_field_prep(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2661 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\
2662 	spx5_field_get(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2666 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\
2667 	FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
2668 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\
2669 	FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
2678 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
2679 	spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2680 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
2681 	spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2685 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
2686 	FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2687 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
2688 	FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2697 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
2698 	spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2699 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
2700 	spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2704 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
2705 	FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2706 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
2707 	FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2715 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\
2716 	FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2717 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\
2718 	FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2721 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\
2722 	FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2723 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\
2724 	FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2732 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
2733 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2734 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2735 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2738 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2739 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2740 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2741 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2749 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\
2750 	FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2751 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\
2752 	FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2760 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\
2761 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2762 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\
2763 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2766 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\
2767 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2768 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\
2769 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2777 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2778 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2779 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2780 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2783 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2784 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2785 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2786 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2789 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2790 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2791 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2792 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2795 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2796 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2797 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2798 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2801 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2802 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2803 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2804 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2807 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2808 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2809 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
2810 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2813 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
2814 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2815 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
2816 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2824 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\
2825 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2826 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\
2827 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2830 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\
2831 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2832 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\
2833 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2836 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\
2837 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2838 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\
2839 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2842 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\
2843 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2844 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\
2845 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2848 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\
2849 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2850 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\
2851 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2859 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
2860 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2861 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
2862 	FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2865 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
2866 	FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2867 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
2868 	FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2871 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
2872 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2873 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
2874 	FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2877 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
2878 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2879 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
2880 	FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2883 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
2884 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2885 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
2886 	FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2889 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
2890 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2891 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
2892 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2895 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
2896 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2897 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
2898 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2901 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
2902 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2903 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
2904 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2907 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
2908 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2909 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
2910 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2923 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\
2924 	FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2925 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\
2926 	FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2934 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\
2935 	FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2936 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\
2937 	FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2940 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\
2941 	FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2942 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\
2943 	FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2951 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
2952 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2953 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2954 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2957 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2958 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2959 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2960 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2968 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2969 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2970 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2971 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2974 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2975 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2976 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2977 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2980 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2981 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2982 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2983 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2986 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2987 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2988 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2989 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2992 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2993 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2994 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2995 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2998 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2999 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3000 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
3001 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3004 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
3005 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3006 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
3007 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3015 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
3016 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3017 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
3018 	FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3021 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
3022 	FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3023 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
3024 	FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3027 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
3028 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3029 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
3030 	FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3033 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
3034 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3035 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
3036 	FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3039 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
3040 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
3041 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
3042 	FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
3045 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
3046 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
3047 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
3048 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
3051 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
3052 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
3053 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
3054 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
3057 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
3058 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
3059 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
3060 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
3063 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
3064 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
3065 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
3066 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
3074 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\
3075 	FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
3076 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\
3077 	FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
3085 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\
3086 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
3087 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\
3088 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
3091 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\
3092 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
3093 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\
3094 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
3097 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\
3098 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
3099 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\
3100 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
3108 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
3109 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3110 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
3111 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3114 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\
3115 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
3116 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\
3117 	FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
3120 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\
3121 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
3122 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\
3123 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
3126 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\
3127 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
3128 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\
3129 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
3132 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
3133 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
3134 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
3135 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
3138 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
3139 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
3140 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
3141 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
3144 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
3145 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
3146 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
3147 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
3150 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
3151 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
3152 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
3153 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
3161 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\
3162 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
3163 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\
3164 	FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
3167 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\
3168 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
3169 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\
3170 	FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
3178 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\
3179 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
3180 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\
3181 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
3184 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
3185 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
3186 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
3187 	FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
3190 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\
3191 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
3192 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\
3193 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
3201 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
3202 	FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
3203 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
3204 	FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
3212 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\
3213 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
3214 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\
3215 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
3218 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\
3219 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
3220 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\
3221 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
3224 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\
3225 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
3226 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\
3227 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
3230 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
3231 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
3232 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
3233 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
3241 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\
3242 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
3243 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\
3244 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
3247 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\
3248 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
3249 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\
3250 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
3258 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\
3259 	FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
3260 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\
3261 	FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
3269 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\
3270 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
3271 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\
3272 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
3275 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\
3276 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
3277 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\
3278 	FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
3281 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\
3282 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
3283 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\
3284 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
3287 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\
3288 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
3289 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\
3290 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
3298 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\
3299 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
3300 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\
3301 	FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
3304 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\
3305 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
3306 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\
3307 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
3310 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\
3311 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
3312 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\
3313 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
3316 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\
3317 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
3318 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\
3319 	FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
3322 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\
3323 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
3324 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\
3325 	FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
3333 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\
3334 	FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
3335 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\
3336 	FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
3339 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\
3340 	FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
3341 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\
3342 	FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
3345 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\
3346 	FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
3347 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\
3348 	FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
3356 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\
3357 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
3358 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\
3359 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
3362 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\
3363 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
3364 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\
3365 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
3368 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
3369 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3370 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
3371 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3379 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\
3380 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3381 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\
3382 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3385 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\
3386 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3387 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\
3388 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3391 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\
3392 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3393 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\
3394 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3402 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
3403 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3404 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
3405 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3408 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
3409 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3410 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
3411 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3414 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\
3415 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3416 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\
3417 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3420 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\
3421 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3422 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\
3423 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3431 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\
3432 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3433 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\
3434 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3437 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\
3438 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3439 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\
3440 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3443 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\
3444 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3445 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\
3446 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3454 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\
3455 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3456 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\
3457 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3460 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\
3461 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3462 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\
3463 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3466 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\
3467 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3468 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\
3469 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3472 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
3473 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3474 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
3475 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3483 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\
3484 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3485 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\
3486 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3489 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\
3490 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3491 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\
3492 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3495 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
3496 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3497 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
3498 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3501 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
3502 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3503 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
3504 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3512 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
3513 	FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3514 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
3515 	FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3518 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\
3519 	FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3520 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\
3521 	FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3529 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\
3530 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3531 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\
3532 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3535 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\
3536 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3537 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\
3538 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3541 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\
3542 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3543 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\
3544 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3547 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\
3548 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3549 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\
3550 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3553 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\
3554 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3555 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\
3556 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3559 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\
3560 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3561 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\
3562 	FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3565 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\
3566 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3567 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\
3568 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3571 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\
3572 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3573 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\
3574 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3577 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\
3578 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3579 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\
3580 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3583 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\
3584 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3585 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\
3586 	FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3589 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\
3590 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3591 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\
3592 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3595 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\
3596 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3597 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\
3598 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3601 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\
3602 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3603 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\
3604 	FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3612 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\
3613 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3614 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\
3615 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3618 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\
3619 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3620 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\
3621 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3624 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\
3625 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3626 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\
3627 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3630 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\
3631 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3632 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\
3633 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3636 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\
3637 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3638 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\
3639 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3642 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\
3643 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3644 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\
3645 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3648 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\
3649 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3650 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\
3651 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3654 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\
3655 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3656 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\
3657 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3664 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\
3665 	FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3666 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\
3667 	FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3670 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\
3671 	FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3672 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\
3673 	FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3680 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
3681 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3682 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
3683 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3686 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
3687 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3688 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
3689 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3697 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
3698 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3699 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
3700 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3703 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
3704 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3705 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
3706 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3709 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
3710 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3711 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
3712 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3715 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
3716 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3717 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
3718 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3721 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
3722 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3723 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
3724 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3727 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
3728 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3729 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
3730 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3733 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
3734 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3735 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
3736 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
4139 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
4140 	FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
4141 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
4142 	FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
4155 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
4156 	FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
4157 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
4158 	FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
4171 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
4172 	FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
4173 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
4174 	FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
4187 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
4188 	FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
4189 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
4190 	FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
4203 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
4204 	FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
4205 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
4206 	FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
4219 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
4220 	FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
4221 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
4222 	FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
4235 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
4236 	FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
4237 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
4238 	FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
4251 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
4252 	FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
4253 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
4254 	FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
4262 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
4263 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
4264 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
4265 	FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
4268 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
4269 	FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
4270 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
4271 	FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
4274 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
4275 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
4276 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
4277 	FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
4280 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
4281 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
4282 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
4283 	FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
4286 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
4287 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
4288 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
4289 	FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
4292 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
4293 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
4294 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
4295 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
4298 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
4299 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
4300 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
4301 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
4304 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
4305 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
4306 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
4307 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
4310 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
4311 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
4312 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
4313 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
4325 #define DSM_RAM_INIT_RAM_INIT_SET(x)\
4326 	FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
4327 #define DSM_RAM_INIT_RAM_INIT_GET(x)\
4328 	FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
4331 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4332 	FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
4333 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4334 	FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
4342 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\
4343 	FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
4344 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\
4345 	FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
4348 #define DSM_BUF_CFG_AGING_ENA_SET(x)\
4349 	FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
4350 #define DSM_BUF_CFG_AGING_ENA_GET(x)\
4351 	FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
4354 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\
4355 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
4356 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\
4357 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
4360 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\
4361 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
4362 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\
4363 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
4371 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\
4372 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
4373 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\
4374 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
4377 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\
4378 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
4379 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\
4380 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
4383 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\
4384 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
4385 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\
4386 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
4389 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\
4390 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
4391 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\
4392 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
4400 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\
4401 	FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
4402 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\
4403 	FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
4406 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\
4407 	FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
4408 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\
4409 	FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
4417 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\
4418 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
4419 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\
4420 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
4423 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\
4424 	FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
4425 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\
4426 	FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
4429 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\
4430 	FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
4431 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\
4432 	FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
4435 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\
4436 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
4437 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\
4438 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
4446 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\
4447 	FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
4448 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\
4449 	FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
4457 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\
4458 	FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
4459 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\
4460 	FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
4468 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\
4469 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
4470 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\
4471 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
4474 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\
4475 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
4476 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\
4477 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
4480 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\
4481 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
4482 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\
4483 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
4486 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\
4487 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4488 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\
4489 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4492 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\
4493 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4494 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
4495 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4499 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\
4500 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
4501 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\
4502 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
4506 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\
4507 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
4508 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\
4509 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
4513 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\
4514 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
4515 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\
4516 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
4524 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\
4525 	FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4526 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\
4527 	FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4530 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\
4531 	FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4532 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\
4533 	FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4536 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\
4537 	FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4538 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\
4539 	FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4542 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\
4543 	FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4544 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\
4545 	FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4558 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\
4559 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4560 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\
4561 	FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4564 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\
4565 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4566 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\
4567 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4570 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\
4571 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4572 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\
4573 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4576 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\
4577 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4578 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\
4579 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4582 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\
4583 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4584 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\
4585 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4588 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\
4589 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4590 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\
4591 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4599 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\
4600 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4601 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\
4602 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4605 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\
4606 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4607 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\
4608 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4611 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\
4612 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4613 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\
4614 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4617 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\
4618 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4619 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\
4620 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4623 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\
4624 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4625 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\
4626 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4629 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\
4630 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4631 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\
4632 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4635 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\
4636 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4637 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\
4638 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4641 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\
4642 	FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4643 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\
4644 	FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4652 #define EACL_RAM_INIT_RAM_INIT_SET(x)\
4653 	FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
4654 #define EACL_RAM_INIT_RAM_INIT_GET(x)\
4655 	FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
4658 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4659 	FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4660 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4661 	FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4669 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
4670 	FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4671 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
4672 	FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4680 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
4681 	FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
4682 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
4683 	FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
4691 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
4692 	FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
4693 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
4694 	FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
4723 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\
4724 	spx5_field_prep(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4725 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\
4726 	spx5_field_get(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4730 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
4731 	spx5_field_prep(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4732 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
4733 	spx5_field_get(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4737 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
4738 	spx5_field_prep(FDMA_CH_CFG_CH_INJ_PORT, x)
4739 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
4740 	spx5_field_get(FDMA_CH_CFG_CH_INJ_PORT, x)
4744 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
4745 	spx5_field_prep(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4746 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
4747 	spx5_field_get(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4750 #define FDMA_CH_CFG_CH_MEM_SET(x)\
4751 	FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
4752 #define FDMA_CH_CFG_CH_MEM_GET(x)\
4753 	FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
4761 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\
4762 	FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
4763 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\
4764 	FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
4772 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\
4773 	FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4774 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\
4775 	FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4778 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\
4779 	FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4780 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\
4781 	FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4789 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
4790 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
4791 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
4792 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
4795 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\
4796 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4797 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\
4798 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4801 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
4802 	FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
4803 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
4804 	FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
4807 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\
4808 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4809 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\
4810 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4813 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\
4814 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4815 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\
4816 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4824 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\
4825 	FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
4826 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\
4827 	FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
4835 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\
4836 	FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4837 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\
4838 	FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4846 #define FDMA_INTR_DB_INTR_DB_SET(x)\
4847 	FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
4848 #define FDMA_INTR_DB_INTR_DB_GET(x)\
4849 	FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
4857 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
4858 	FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4859 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
4860 	FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4868 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\
4869 	FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4870 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\
4871 	FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4874 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\
4875 	FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
4876 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\
4877 	FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
4885 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\
4886 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
4887 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\
4888 	FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
4891 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\
4892 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
4893 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\
4894 	FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
4897 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\
4898 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4899 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\
4900 	FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4903 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\
4904 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4905 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\
4906 	FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4909 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\
4910 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
4911 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\
4912 	FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
4915 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\
4916 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
4917 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\
4918 	FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
4921 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\
4922 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4923 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\
4924 	FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4927 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\
4928 	FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
4929 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\
4930 	FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
4938 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\
4939 	FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4940 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\
4941 	FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4949 #define FDMA_CTRL_NRESET_SET(x)\
4950 	FIELD_PREP(FDMA_CTRL_NRESET, x)
4951 #define FDMA_CTRL_NRESET_GET(x)\
4952 	FIELD_GET(FDMA_CTRL_NRESET, x)
4960 #define GCB_CHIP_ID_REV_ID_SET(x)\
4961 	FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
4962 #define GCB_CHIP_ID_REV_ID_GET(x)\
4963 	FIELD_GET(GCB_CHIP_ID_REV_ID, x)
4966 #define GCB_CHIP_ID_PART_ID_SET(x)\
4967 	FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
4968 #define GCB_CHIP_ID_PART_ID_GET(x)\
4969 	FIELD_GET(GCB_CHIP_ID_PART_ID, x)
4972 #define GCB_CHIP_ID_MFG_ID_SET(x)\
4973 	FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
4974 #define GCB_CHIP_ID_MFG_ID_GET(x)\
4975 	FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
4978 #define GCB_CHIP_ID_ONE_SET(x)\
4979 	FIELD_PREP(GCB_CHIP_ID_ONE, x)
4980 #define GCB_CHIP_ID_ONE_GET(x)\
4981 	FIELD_GET(GCB_CHIP_ID_ONE, x)
4990 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\
4991 	FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4992 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\
4993 	FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4996 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\
4997 	FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
4998 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\
4999 	FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
5002 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\
5003 	FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
5004 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\
5005 	FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
5014 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\
5015 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
5016 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\
5017 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
5020 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\
5021 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
5022 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\
5023 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
5033 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\
5034 	spx5_field_prep(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
5035 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\
5036 	spx5_field_get(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
5044 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\
5045 	FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
5046 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\
5047 	FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
5050 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\
5051 	FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
5052 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\
5053 	FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
5061 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\
5062 	FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x)
5063 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\
5064 	FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x)
5067 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\
5068 	FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x)
5069 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\
5070 	FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x)
5078 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\
5079 	FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x)
5080 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\
5081 	FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x)
5084 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\
5085 	FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x)
5086 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\
5087 	FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x)
5096 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\
5097 	spx5_field_prep(HSCH_SE_CFG_SE_DWRR_CNT, x)
5098 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\
5099 	spx5_field_get(HSCH_SE_CFG_SE_DWRR_CNT, x)
5102 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\
5103 	FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x)
5104 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\
5105 	FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x)
5108 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\
5109 	FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x)
5110 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\
5111 	FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x)
5114 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\
5115 	FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
5116 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\
5117 	FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
5120 #define HSCH_SE_CFG_SE_STOP_SET(x)\
5121 	FIELD_PREP(HSCH_SE_CFG_SE_STOP, x)
5122 #define HSCH_SE_CFG_SE_STOP_GET(x)\
5123 	FIELD_GET(HSCH_SE_CFG_SE_STOP, x)
5132 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\
5133 	spx5_field_prep(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
5134 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\
5135 	spx5_field_get(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
5143 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\
5144 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
5145 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\
5146 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
5150 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\
5151 	spx5_field_prep(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
5152 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\
5153 	spx5_field_get(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
5156 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\
5157 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
5158 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\
5159 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
5162 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\
5163 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
5164 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\
5165 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
5168 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\
5169 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
5170 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\
5171 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
5179 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\
5180 	FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x)
5181 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\
5182 	FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x)
5185 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\
5186 	FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
5187 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\
5188 	FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
5197 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\
5198 	spx5_field_prep(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
5199 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\
5200 	spx5_field_get(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
5203 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\
5204 	FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
5205 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\
5206 	FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
5209 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\
5210 	FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
5211 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\
5212 	FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
5221 #define HSCH_SYS_CLK_PER_100PS_SET(x)\
5222 	FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x)
5223 #define HSCH_SYS_CLK_PER_100PS_GET(x)\
5224 	FIELD_GET(HSCH_SYS_CLK_PER_100PS, x)
5232 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\
5233 	FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
5234 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\
5235 	FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
5244 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\
5245 	spx5_field_prep(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
5246 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\
5247 	spx5_field_get(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
5250 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\
5251 	FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
5252 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\
5253 	FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
5261 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\
5262 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
5263 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\
5264 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
5267 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\
5268 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
5269 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\
5270 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
5273 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\
5274 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
5275 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\
5276 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
5280 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\
5281 	spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
5282 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\
5283 	spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
5286 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\
5287 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
5288 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\
5289 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
5292 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\
5293 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
5294 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\
5295 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
5299 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\
5300 	spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
5301 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\
5302 	spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
5310 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\
5311 	FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
5312 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\
5313 	FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
5316 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\
5317 	FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
5318 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\
5319 	FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
5322 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\
5323 	FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
5324 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\
5325 	FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
5328 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\
5329 	FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
5330 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\
5331 	FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
5334 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\
5335 	FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
5336 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\
5337 	FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
5345 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\
5346 	FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
5347 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\
5348 	FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
5356 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\
5357 	FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
5358 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\
5359 	FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
5367 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\
5368 	FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
5369 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\
5370 	FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
5378 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\
5379 	FIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)
5380 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\
5381 	FIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)
5389 #define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\
5390 	FIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)
5391 #define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\
5392 	FIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)
5395 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(x)\
5396 	FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x)
5397 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_GET(x)\
5398 	FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x)
5401 #define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(x)\
5402 	FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x)
5403 #define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_GET(x)\
5404 	FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x)
5412 #define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\
5413 	FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x)
5414 #define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\
5415 	FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x)
5418 #define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\
5419 	FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)
5420 #define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\
5421 	FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)
5424 #define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\
5425 	FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)
5426 #define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\
5427 	FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)
5430 #define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\
5431 	FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x)
5432 #define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\
5433 	FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x)
5440 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\
5441 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
5442 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\
5443 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
5446 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\
5447 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
5448 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\
5449 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
5453 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\
5454 	spx5_field_prep(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
5455 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\
5456 	spx5_field_get(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
5459 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\
5460 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
5461 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\
5462 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
5465 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\
5466 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
5467 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\
5468 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
5475 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\
5476 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
5477 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\
5478 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
5481 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\
5482 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
5483 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\
5484 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
5495 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\
5496 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
5497 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\
5498 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
5501 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\
5502 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
5503 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\
5504 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
5507 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\
5508 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
5509 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\
5510 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
5513 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\
5514 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
5515 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\
5516 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
5519 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\
5520 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
5521 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\
5522 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
5525 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\
5526 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
5527 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\
5528 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
5531 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\
5532 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
5533 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\
5534 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
5537 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\
5538 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
5539 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\
5540 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
5543 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\
5544 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
5545 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\
5546 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
5549 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\
5550 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
5551 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\
5552 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
5555 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\
5556 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
5557 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\
5558 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
5561 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\
5562 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
5563 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\
5564 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
5572 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\
5573 	spx5_field_prep(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
5574 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\
5575 	spx5_field_get(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
5582 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\
5583 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
5584 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\
5585 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
5588 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\
5589 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
5590 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\
5591 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
5594 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\
5595 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
5596 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\
5597 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
5600 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\
5601 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
5602 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\
5603 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
5606 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\
5607 	FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
5608 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\
5609 	FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
5612 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\
5613 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
5614 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\
5615 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
5618 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\
5619 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
5620 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\
5621 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
5624 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\
5625 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
5626 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\
5627 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
5630 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\
5631 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5632 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\
5633 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5636 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\
5637 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5638 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\
5639 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5642 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\
5643 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5644 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\
5645 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5648 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\
5649 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5650 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\
5651 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5654 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\
5655 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5656 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\
5657 	FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5660 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\
5661 	FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5662 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\
5663 	FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5666 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\
5667 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5668 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\
5669 	FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5676 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\
5677 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5678 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\
5679 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5682 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\
5683 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5684 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\
5685 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5692 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\
5693 	FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5694 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\
5695 	FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5698 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\
5699 	FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5700 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\
5701 	FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5708 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\
5709 	FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5710 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\
5711 	FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5714 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\
5715 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5716 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\
5717 	FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5720 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\
5721 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5722 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\
5723 	FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5726 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\
5727 	FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5728 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\
5729 	FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5732 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\
5733 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5734 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\
5735 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5738 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\
5739 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5740 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\
5741 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5744 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\
5745 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5746 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\
5747 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5755 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\
5756 	spx5_field_prep(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5757 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\
5758 	spx5_field_get(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5761 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\
5762 	FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5763 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\
5764 	FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5772 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\
5773 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5774 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\
5775 	FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5778 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\
5779 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
5780 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\
5781 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
5784 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\
5785 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5786 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\
5787 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5790 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\
5791 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5792 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\
5793 	FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5796 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\
5797 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
5798 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\
5799 	FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
5802 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\
5803 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5804 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\
5805 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5808 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\
5809 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5810 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\
5811 	FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5814 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\
5815 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5816 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\
5817 	FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5820 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\
5821 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5822 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\
5823 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5826 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\
5827 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5828 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\
5829 	FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5837 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\
5838 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5839 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\
5840 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5843 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\
5844 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5845 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\
5846 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5859 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\
5860 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5861 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\
5862 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5865 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\
5866 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5867 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\
5868 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5886 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\
5887 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5888 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\
5889 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5892 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\
5893 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5894 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\
5895 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5903 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\
5904 	FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5905 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\
5906 	FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5909 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
5910 	FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5911 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
5912 	FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5915 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
5916 	FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5917 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
5918 	FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5921 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
5922 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5923 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
5924 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5927 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
5928 	FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5929 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
5930 	FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5933 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
5934 	FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5935 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
5936 	FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5939 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
5940 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5941 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
5942 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5945 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
5946 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5947 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
5948 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5951 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
5952 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5953 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
5954 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5957 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
5958 	FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5959 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
5960 	FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5963 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
5964 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5965 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
5966 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5969 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
5970 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5971 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
5972 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5980 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
5981 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5982 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
5983 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5986 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\
5987 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5988 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\
5989 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5992 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
5993 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
5994 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
5995 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
6003 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\
6004 	FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
6005 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\
6006 	FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
6009 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
6010 	FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
6011 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
6012 	FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
6015 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
6016 	FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
6017 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
6018 	FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
6021 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
6022 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
6023 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
6024 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
6027 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
6028 	FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
6029 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
6030 	FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
6033 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
6034 	FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
6035 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
6036 	FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
6039 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
6040 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
6041 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
6042 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
6045 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
6046 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
6047 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
6048 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
6051 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
6052 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
6053 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
6054 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
6057 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
6058 	FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
6059 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
6060 	FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
6063 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
6064 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
6065 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
6066 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
6069 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
6070 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6071 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
6072 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6080 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
6081 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
6082 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
6083 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
6086 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\
6087 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
6088 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\
6089 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
6092 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
6093 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
6094 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
6095 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
6103 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\
6104 	FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
6105 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\
6106 	FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
6109 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
6110 	FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
6111 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
6112 	FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
6115 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
6116 	FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
6117 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
6118 	FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
6121 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
6122 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
6123 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
6124 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
6127 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
6128 	FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
6129 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
6130 	FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
6133 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
6134 	FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
6135 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
6136 	FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
6139 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
6140 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
6141 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
6142 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
6145 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
6146 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
6147 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
6148 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
6151 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
6152 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
6153 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
6154 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
6157 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
6158 	FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
6159 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
6160 	FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
6163 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
6164 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
6165 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
6166 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
6169 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
6170 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6171 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
6172 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6180 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
6181 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
6182 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
6183 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
6186 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\
6187 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
6188 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\
6189 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
6192 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
6193 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
6194 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
6195 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
6203 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\
6204 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
6205 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\
6206 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
6210 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\
6211 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
6212 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\
6213 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
6217 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\
6218 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
6219 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\
6220 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
6224 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\
6225 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
6226 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\
6227 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
6231 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\
6232 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
6233 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\
6234 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
6238 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\
6239 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
6240 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\
6241 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
6245 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\
6246 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
6247 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\
6248 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
6252 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\
6253 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
6254 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\
6255 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
6259 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\
6260 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
6261 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\
6262 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
6265 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\
6266 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
6267 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\
6268 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
6272 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\
6273 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
6274 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\
6275 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
6279 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\
6280 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
6281 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\
6282 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
6286 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\
6287 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
6288 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\
6289 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
6296 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\
6297 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
6298 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\
6299 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
6303 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\
6304 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
6305 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\
6306 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
6310 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\
6311 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
6312 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\
6313 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
6317 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\
6318 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
6319 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\
6320 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
6324 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\
6325 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
6326 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\
6327 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
6331 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\
6332 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
6333 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\
6334 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
6338 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\
6339 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
6340 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\
6341 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
6345 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\
6346 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
6347 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\
6348 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
6352 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\
6353 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
6354 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\
6355 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
6359 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\
6360 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
6361 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\
6362 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
6366 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\
6367 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
6368 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\
6369 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
6373 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\
6374 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
6375 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\
6376 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
6384 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\
6385 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
6386 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\
6387 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
6390 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\
6391 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
6392 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\
6393 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
6396 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\
6397 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
6398 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\
6399 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
6402 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\
6403 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
6404 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\
6405 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
6408 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\
6409 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
6410 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\
6411 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
6414 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\
6415 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
6416 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\
6417 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
6420 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\
6421 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
6422 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\
6423 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
6426 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\
6427 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
6428 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\
6429 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
6436 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\
6437 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
6438 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\
6439 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
6442 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\
6443 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
6444 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\
6445 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
6448 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\
6449 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
6450 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\
6451 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
6454 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\
6455 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
6456 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\
6457 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
6460 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\
6461 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
6462 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\
6463 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
6466 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\
6467 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
6468 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\
6469 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
6473 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\
6474 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
6475 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\
6476 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
6480 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\
6481 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
6482 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\
6483 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
6487 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\
6488 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
6489 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\
6490 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
6494 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\
6495 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
6496 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\
6497 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
6501 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\
6502 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
6503 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\
6504 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
6508 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\
6509 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
6510 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\
6511 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
6519 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\
6520 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
6521 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\
6522 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
6525 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\
6526 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
6527 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\
6528 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
6531 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\
6532 	FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
6533 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\
6534 	FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
6537 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\
6538 	FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
6539 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\
6540 	FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
6543 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\
6544 	FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
6545 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\
6546 	FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
6549 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\
6550 	FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
6551 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\
6552 	FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
6555 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\
6556 	FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
6557 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\
6558 	FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
6567 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\
6568 	spx5_field_prep(PTP_PTP_PIN_INTR_INTR_PTP, x)
6569 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\
6570 	spx5_field_get(PTP_PTP_PIN_INTR_INTR_PTP, x)
6579 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\
6580 	spx5_field_prep(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
6581 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\
6582 	spx5_field_get(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
6591 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\
6592 	spx5_field_prep(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
6593 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\
6594 	spx5_field_get(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
6602 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\
6603 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
6604 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\
6605 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
6608 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\
6609 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x)
6610 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\
6611 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x)
6614 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\
6615 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
6616 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\
6617 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
6620 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\
6621 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
6622 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\
6623 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
6636 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\
6637 	FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
6638 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\
6639 	FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
6647 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\
6648 	FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
6649 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\
6650 	FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
6663 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\
6664 	FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
6665 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\
6666 	FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
6680 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\
6681 	spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
6682 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\
6683 	spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
6687 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\
6688 	spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
6689 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\
6690 	spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
6694 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\
6695 	spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6696 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\
6697 	spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6701 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\
6702 	spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6703 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\
6704 	spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6707 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\
6708 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6709 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\
6710 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6713 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\
6714 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6715 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\
6716 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6719 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\
6720 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6721 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\
6722 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6725 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\
6726 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6727 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\
6728 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6731 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\
6732 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6733 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\
6734 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6742 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\
6743 	FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6744 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\
6745 	FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6758 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\
6759 	FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6760 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\
6761 	FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6769 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\
6770 	FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6771 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\
6772 	FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6785 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\
6786 	FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6787 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\
6788 	FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6796 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\
6797 	FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6798 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\
6799 	FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6807 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\
6808 	FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6809 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\
6810 	FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6813 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\
6814 	FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6815 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\
6816 	FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6826 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\
6827 	spx5_field_prep(PTP_PHAD_CTRL_PHAD_ENA, x)
6828 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\
6829 	spx5_field_get(PTP_PHAD_CTRL_PHAD_ENA, x)
6833 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\
6834 	spx5_field_prep(PTP_PHAD_CTRL_PHAD_FAILED, x)
6835 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\
6836 	spx5_field_get(PTP_PHAD_CTRL_PHAD_FAILED, x)
6840 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\
6841 	FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x)
6842 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\
6843 	FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x)
6846 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\
6847 	FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x)
6848 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\
6849 	FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x)
6863 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
6864 	FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6865 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
6866 	FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6869 #define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
6870 	FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x)
6871 #define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
6872 	FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x)
6875 #define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
6876 	FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x)
6877 #define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
6878 	FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x)
6881 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
6882 	FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x)
6883 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
6884 	FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x)
6887 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
6888 	FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6889 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
6890 	FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6893 #define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
6894 	FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6895 #define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
6896 	FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6904 #define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\
6905 	FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x)
6906 #define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\
6907 	FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x)
6915 #define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\
6916 	FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x)
6917 #define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\
6918 	FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x)
6926 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\
6927 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6928 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\
6929 	FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6932 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\
6933 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6934 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\
6935 	FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6938 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\
6939 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6940 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\
6941 	FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6944 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
6945 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6946 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
6947 	FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6950 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\
6951 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6952 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\
6953 	FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6956 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\
6957 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6958 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\
6959 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6962 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\
6963 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6964 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\
6965 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6968 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\
6969 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6970 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\
6971 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6974 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\
6975 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6976 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\
6977 	FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6985 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\
6986 	spx5_field_prep(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)
6987 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\
6988 	spx5_field_get(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)
6996 #define QRES_RES_CFG_WM_HIGH_SET(x)\
6997 	spx5_field_prep(QRES_RES_CFG_WM_HIGH, x)
6998 #define QRES_RES_CFG_WM_HIGH_GET(x)\
6999 	spx5_field_get(QRES_RES_CFG_WM_HIGH, x)
7007 #define QRES_RES_STAT_MAXUSE_SET(x)\
7008 	spx5_field_prep(QRES_RES_STAT_MAXUSE, x)
7009 #define QRES_RES_STAT_MAXUSE_GET(x)\
7010 	spx5_field_get(QRES_RES_STAT_MAXUSE, x)
7018 #define QRES_RES_STAT_CUR_INUSE_SET(x)\
7019 	spx5_field_prep(QRES_RES_STAT_CUR_INUSE, x)
7020 #define QRES_RES_STAT_CUR_INUSE_GET(x)\
7021 	spx5_field_get(QRES_RES_STAT_CUR_INUSE, x)
7028 #define QS_XTR_GRP_CFG_MODE_SET(x)\
7029 	FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
7030 #define QS_XTR_GRP_CFG_MODE_GET(x)\
7031 	FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
7034 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\
7035 	FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
7036 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\
7037 	FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
7040 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
7041 	FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
7042 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
7043 	FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
7054 #define QS_XTR_FLUSH_FLUSH_SET(x)\
7055 	FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
7056 #define QS_XTR_FLUSH_FLUSH_GET(x)\
7057 	FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
7064 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\
7065 	FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
7066 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\
7067 	FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
7074 #define QS_INJ_GRP_CFG_MODE_SET(x)\
7075 	FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
7076 #define QS_INJ_GRP_CFG_MODE_GET(x)\
7077 	FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
7080 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
7081 	FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
7082 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
7083 	FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
7094 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\
7095 	FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
7096 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\
7097 	FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
7100 #define QS_INJ_CTRL_ABORT_SET(x)\
7101 	FIELD_PREP(QS_INJ_CTRL_ABORT, x)
7102 #define QS_INJ_CTRL_ABORT_GET(x)\
7103 	FIELD_GET(QS_INJ_CTRL_ABORT, x)
7106 #define QS_INJ_CTRL_EOF_SET(x)\
7107 	FIELD_PREP(QS_INJ_CTRL_EOF, x)
7108 #define QS_INJ_CTRL_EOF_GET(x)\
7109 	FIELD_GET(QS_INJ_CTRL_EOF, x)
7112 #define QS_INJ_CTRL_SOF_SET(x)\
7113 	FIELD_PREP(QS_INJ_CTRL_SOF, x)
7114 #define QS_INJ_CTRL_SOF_GET(x)\
7115 	FIELD_GET(QS_INJ_CTRL_SOF, x)
7118 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\
7119 	FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
7120 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\
7121 	FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
7128 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
7129 	FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
7130 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
7131 	FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
7134 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\
7135 	FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
7136 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\
7137 	FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
7140 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\
7141 	FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
7142 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\
7143 	FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
7152 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\
7153 	spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_START, x)
7154 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\
7155 	spx5_field_get(QSYS_PAUSE_CFG_PAUSE_START, x)
7159 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
7160 	spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_STOP, x)
7161 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
7162 	spx5_field_get(QSYS_PAUSE_CFG_PAUSE_STOP, x)
7165 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
7166 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
7167 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
7168 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
7171 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\
7172 	FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
7173 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\
7174 	FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
7183 #define QSYS_ATOP_ATOP_SET(x)\
7184 	spx5_field_prep(QSYS_ATOP_ATOP, x)
7185 #define QSYS_ATOP_ATOP_GET(x)\
7186 	spx5_field_get(QSYS_ATOP_ATOP, x)
7194 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\
7195 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
7196 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\
7197 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
7200 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\
7201 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
7202 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\
7203 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
7212 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\
7213 	spx5_field_prep(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
7214 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\
7215 	spx5_field_get(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
7223 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\
7224 	FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
7225 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\
7226 	FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
7234 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\
7235 	FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
7236 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\
7237 	FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
7240 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\
7241 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
7242 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\
7243 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
7246 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\
7247 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
7248 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\
7249 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
7257 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\
7258 	FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
7259 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\
7260 	FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
7263 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\
7264 	FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
7265 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\
7266 	FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
7274 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\
7275 	FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
7276 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\
7277 	FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
7286 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\
7287 	spx5_field_prep(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
7288 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\
7289 	spx5_field_get(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
7292 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\
7293 	FIELD_PREP(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
7294 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\
7295 	FIELD_GET(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
7298 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\
7299 	FIELD_PREP(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
7300 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\
7301 	FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
7309 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\
7310 	FIELD_PREP(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
7311 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\
7312 	FIELD_GET(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
7315 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\
7316 	FIELD_PREP(REW_ES0_CTRL_ES0_BY_RLEG, x)
7317 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\
7318 	FIELD_GET(REW_ES0_CTRL_ES0_BY_RLEG, x)
7321 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\
7322 	FIELD_PREP(REW_ES0_CTRL_ES0_DPORT_ENA, x)
7323 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\
7324 	FIELD_GET(REW_ES0_CTRL_ES0_DPORT_ENA, x)
7327 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\
7328 	FIELD_PREP(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
7329 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\
7330 	FIELD_GET(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
7333 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\
7334 	FIELD_PREP(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
7335 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\
7336 	FIELD_GET(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
7339 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\
7340 	FIELD_PREP(REW_ES0_CTRL_ES0_LU_ENA, x)
7341 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\
7342 	FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x)
7350 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\
7351 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
7352 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\
7353 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
7356 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\
7357 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
7358 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\
7359 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
7362 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
7363 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
7364 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
7365 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
7373 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\
7374 	FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x)
7375 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\
7376 	FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x)
7384 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\
7385 	FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x)
7386 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\
7387 	FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x)
7395 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\
7396 	FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x)
7397 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\
7398 	FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x)
7406 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\
7407 	FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x)
7408 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\
7409 	FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x)
7417 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\
7418 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
7419 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\
7420 	FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
7423 #define REW_TAG_CTRL_TAG_CFG_SET(x)\
7424 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
7425 #define REW_TAG_CTRL_TAG_CFG_GET(x)\
7426 	FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
7429 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\
7430 	FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
7431 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\
7432 	FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
7435 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\
7436 	FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
7437 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\
7438 	FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
7441 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\
7442 	FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
7443 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\
7444 	FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
7447 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\
7448 	FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
7449 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\
7450 	FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
7458 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\
7459 	FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
7460 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\
7461 	FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
7464 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\
7465 	FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
7466 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\
7467 	FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
7475 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
7476 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
7477 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
7478 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
7481 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
7482 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
7483 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
7484 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
7487 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
7488 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
7489 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
7490 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
7493 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
7494 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
7495 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
7496 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
7499 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
7500 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
7501 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
7502 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
7505 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
7506 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
7507 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
7508 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
7516 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
7517 	FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
7518 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
7519 	FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
7527 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\
7528 	FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
7529 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\
7530 	FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
7548 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\
7549 	FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
7550 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\
7551 	FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
7559 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\
7560 	FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
7561 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\
7562 	FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
7565 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\
7566 	FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
7567 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\
7568 	FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
7576 #define REW_RAM_INIT_RAM_INIT_SET(x)\
7577 	FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
7578 #define REW_RAM_INIT_RAM_INIT_GET(x)\
7579 	FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
7582 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\
7583 	FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
7584 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\
7585 	FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
7592 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\
7593 	FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CMD, x)
7594 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\
7595 	FIELD_GET(VCAP_ES0_CTRL_UPDATE_CMD, x)
7598 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\
7599 	FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
7600 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\
7601 	FIELD_GET(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
7604 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\
7605 	FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
7606 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\
7607 	FIELD_GET(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
7610 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\
7611 	FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
7612 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\
7613 	FIELD_GET(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
7616 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\
7617 	FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ADDR, x)
7618 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\
7619 	FIELD_GET(VCAP_ES0_CTRL_UPDATE_ADDR, x)
7622 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\
7623 	FIELD_PREP(VCAP_ES0_CTRL_UPDATE_SHOT, x)
7624 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\
7625 	FIELD_GET(VCAP_ES0_CTRL_UPDATE_SHOT, x)
7628 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\
7629 	FIELD_PREP(VCAP_ES0_CTRL_CLEAR_CACHE, x)
7630 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\
7631 	FIELD_GET(VCAP_ES0_CTRL_CLEAR_CACHE, x)
7634 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\
7635 	FIELD_PREP(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
7636 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\
7637 	FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
7644 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\
7645 	FIELD_PREP(VCAP_ES0_CFG_MV_NUM_POS, x)
7646 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\
7647 	FIELD_GET(VCAP_ES0_CFG_MV_NUM_POS, x)
7650 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\
7651 	FIELD_PREP(VCAP_ES0_CFG_MV_SIZE, x)
7652 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\
7653 	FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x)
7684 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\
7685 	FIELD_PREP(VCAP_ES0_IDX_CORE_IDX, x)
7686 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\
7687 	FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x)
7694 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\
7695 	FIELD_PREP(VCAP_ES0_MAP_CORE_MAP, x)
7696 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\
7697 	FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x)
7704 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\
7705 	FIELD_PREP(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7706 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\
7707 	FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7754 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\
7755 	FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x)
7756 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\
7757 	FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x)
7760 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\
7761 	FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
7762 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\
7763 	FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
7766 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\
7767 	FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
7768 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\
7769 	FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
7772 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\
7773 	FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
7774 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\
7775 	FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
7778 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\
7779 	FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x)
7780 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\
7781 	FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x)
7784 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\
7785 	FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x)
7786 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\
7787 	FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x)
7790 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\
7791 	FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x)
7792 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\
7793 	FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x)
7796 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\
7797 	FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
7798 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\
7799 	FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
7806 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\
7807 	FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x)
7808 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\
7809 	FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x)
7812 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\
7813 	FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x)
7814 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\
7815 	FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x)
7846 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\
7847 	FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x)
7848 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\
7849 	FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x)
7856 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\
7857 	FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x)
7858 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\
7859 	FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x)
7866 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\
7867 	FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7868 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\
7869 	FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7916 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\
7917 	FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7918 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\
7919 	FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7922 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\
7923 	FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7924 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\
7925 	FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7928 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\
7929 	FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7930 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\
7931 	FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7934 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\
7935 	FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7936 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\
7937 	FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7940 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\
7941 	FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7942 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\
7943 	FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7946 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\
7947 	FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7948 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\
7949 	FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7952 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\
7953 	FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7954 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\
7955 	FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7958 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\
7959 	FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7960 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\
7961 	FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7968 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\
7969 	FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x)
7970 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\
7971 	FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x)
7974 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\
7975 	FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x)
7976 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\
7977 	FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x)
8008 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\
8009 	FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x)
8010 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\
8011 	FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x)
8018 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\
8019 	FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x)
8020 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\
8021 	FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x)
8068 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\
8069 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
8070 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\
8071 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
8074 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\
8075 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
8076 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\
8077 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
8085 #define VOP_RAM_INIT_RAM_INIT_SET(x)\
8086 	FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
8087 #define VOP_RAM_INIT_RAM_INIT_GET(x)\
8088 	FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
8091 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\
8092 	FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
8093 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\
8094 	FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
8102 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\
8103 	FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
8104 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\
8105 	FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
8109 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\
8110 	spx5_field_prep(XQS_STAT_CFG_STAT_VIEW, x)
8111 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\
8112 	spx5_field_get(XQS_STAT_CFG_STAT_VIEW, x)
8115 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\
8116 	FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
8117 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\
8118 	FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
8121 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\
8122 	FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
8123 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\
8124 	FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
8133 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\
8134 	spx5_field_prep(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
8135 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\
8136 	spx5_field_get(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
8145 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\
8146 	spx5_field_prep(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
8147 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\
8148 	spx5_field_get(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
8157 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\
8158 	spx5_field_prep(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
8159 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\
8160 	spx5_field_get(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
8169 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\
8170 	spx5_field_prep(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
8171 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\
8172 	spx5_field_get(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
8184 #define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\
8185 	FIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)
8186 #define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\
8187 	FIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)
8195 #define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\
8196 	FIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)
8197 #define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\
8198 	FIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)
8201 #define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\
8202 	FIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)
8203 #define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\
8204 	FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)
8212 #define DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(x)\
8213 	FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x)
8214 #define DEVRGMII_MAC_TAGS_CFG_TAG_ID_GET(x)\
8215 	FIELD_GET(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x)
8218 #define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\
8219 	FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
8220 #define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\
8221 	FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
8224 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(x)\
8225 	FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x)
8226 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA_GET(x)\
8227 	FIELD_GET(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x)
8230 #define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
8231 	FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
8232 #define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
8233 	FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
8241 #define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\
8242 	FIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)
8243 #define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\
8244 	FIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)
8247 #define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\
8248 	FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)
8249 #define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\
8250 	FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)
8253 #define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\
8254 	FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)
8255 #define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\
8256 	FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)