microchip/sparx5/sparx5_calendar.c

37 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5)
39 	switch (sparx5->target_ct) {
118 enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno)
122 	if (portno >= sparx5->data->consts->n_ports) {
125 			    sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) ||
127 			    sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1)) {
131 			   sparx5_get_internal_port(sparx5, SPX5_PORT_VD0)) {
135 			   sparx5_get_internal_port(sparx5, SPX5_PORT_VD1)) {
139 			   sparx5_get_internal_port(sparx5, SPX5_PORT_VD2)) {
147 	port = sparx5->ports[portno];
154 int sparx5_config_auto_calendar(struct sparx5 *sparx5)
156 	const struct sparx5_consts *consts = sparx5->data->consts;
165 	max_core_bw = sparx5_clk_to_bandwidth(sparx5->coreclock);
167 		dev_err(sparx5->dev, "Core clock not supported");
175 		spd = sparx5_get_port_cal_speed(sparx5, portno);
191 	if (used_port_bw > sparx5_target_bandwidth(sparx5)) {
192 		dev_err(sparx5->dev,
194 			used_port_bw, sparx5_target_bandwidth(sparx5));
199 		dev_err(sparx5->dev,
206 	if (is_sparx5(sparx5))
209 			 sparx5, QSYS_CAL_CTRL);
213 		spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx));
220 		 sparx5,
226 			sparx5,
232 		 sparx5, QSYS_CAL_CTRL);
235 	value = spx5_rd(sparx5, QSYS_CAL_CTRL);
237 		dev_err(sparx5->dev, "QSYS calendar error\n");
277 int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
285 	clk_period_ps = sparx5_clk_period(sparx5->coreclock);
303 		if (portno < sparx5->data->consts->n_ports_all) {
305 				(sparx5_get_port_cal_speed(sparx5, portno));
329 		dev_err(sparx5->dev,
368 				dev_err(sparx5->dev,
376 			dev_err(sparx5->dev,
454 				dev_err(sparx5->dev,
473 static int sparx5_dsm_calendar_check(struct sparx5 *sparx5,
523 	dev_err(sparx5->dev,
529 static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi,
534 	if (!is_sparx5(sparx5)) {
537 		val = spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi));
542 			 sparx5, DSM_TAXI_CAL_CFG(taxi));
547 		 sparx5,
552 			 sparx5,
556 			 sparx5,
561 		 sparx5,
563 	len = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(spx5_rd(sparx5,
568 	if (!is_sparx5(sparx5)) {
571 			 sparx5, DSM_TAXI_CAL_CFG(taxi));
576 	dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len);
581 int sparx5_config_dsm_calendar(struct sparx5 *sparx5)
583 	const struct sparx5_ops *ops = sparx5->data->ops;
592 	for (taxi = 0; taxi < sparx5->data->consts->n_dsm_cal_taxis; ++taxi) {
593 		err = ops->dsm_calendar_calc(sparx5, taxi, data);
595 			dev_err(sparx5->dev, "DSM calendar calculation failed\n");
598 		err = sparx5_dsm_calendar_check(sparx5, data);
600 			dev_err(sparx5->dev, "DSM calendar check failed\n");
603 		err = sparx5_dsm_calendar_update(sparx5, taxi, data);
605 			dev_err(sparx5->dev, "DSM calendar update failed\n");