Lines Matching full:x
38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\
39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\
41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\
48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\
50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
53 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\
54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
55 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\
56 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x)
62 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\
63 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
64 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\
65 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x)
74 #define ANA_ANAINTR_INTR_SET(x)\
75 FIELD_PREP(ANA_ANAINTR_INTR, x)
76 #define ANA_ANAINTR_INTR_GET(x)\
77 FIELD_GET(ANA_ANAINTR_INTR, x)
80 #define ANA_ANAINTR_INTR_ENA_SET(x)\
81 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
82 #define ANA_ANAINTR_INTR_ENA_GET(x)\
83 FIELD_GET(ANA_ANAINTR_INTR_ENA, x)
89 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\
90 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
91 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\
92 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x)
98 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\
99 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x)
100 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\
101 FIELD_GET(ANA_MIRRORPORTS_MIRRORPORTS, x)
107 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\
108 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x)
109 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\
110 FIELD_GET(ANA_EMIRRORPORTS_EMIRRORPORTS, x)
116 #define ANA_FLOODING_FLD_UNICAST_SET(x)\
117 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x)
118 #define ANA_FLOODING_FLD_UNICAST_GET(x)\
119 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x)
122 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\
123 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x)
124 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\
125 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x)
128 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\
129 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x)
130 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\
131 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x)
137 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\
138 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
139 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\
140 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
143 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\
144 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
145 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\
146 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
149 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\
150 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
151 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\
152 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
155 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\
156 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
157 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\
158 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
164 #define ANA_PGID_PGID_SET(x)\
165 FIELD_PREP(ANA_PGID_PGID, x)
166 #define ANA_PGID_PGID_GET(x)\
167 FIELD_GET(ANA_PGID_PGID, x)
173 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\
174 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x)
175 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\
176 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x)
188 #define ANA_MACACCESS_CHANGE2SW_SET(x)\
189 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x)
190 #define ANA_MACACCESS_CHANGE2SW_GET(x)\
191 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x)
194 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\
195 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x)
196 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\
197 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x)
200 #define ANA_MACACCESS_VALID_SET(x)\
201 FIELD_PREP(ANA_MACACCESS_VALID, x)
202 #define ANA_MACACCESS_VALID_GET(x)\
203 FIELD_GET(ANA_MACACCESS_VALID, x)
206 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\
207 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x)
208 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\
209 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x)
212 #define ANA_MACACCESS_DEST_IDX_SET(x)\
213 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x)
214 #define ANA_MACACCESS_DEST_IDX_GET(x)\
215 FIELD_GET(ANA_MACACCESS_DEST_IDX, x)
218 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\
219 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x)
220 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\
221 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x)
227 #define ANA_MACTINDX_BUCKET_SET(x)\
228 FIELD_PREP(ANA_MACTINDX_BUCKET, x)
229 #define ANA_MACTINDX_BUCKET_GET(x)\
230 FIELD_GET(ANA_MACTINDX_BUCKET, x)
233 #define ANA_MACTINDX_M_INDEX_SET(x)\
234 FIELD_PREP(ANA_MACTINDX_M_INDEX, x)
235 #define ANA_MACTINDX_M_INDEX_GET(x)\
236 FIELD_GET(ANA_MACTINDX_M_INDEX, x)
242 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\
243 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)
244 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\
245 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)
251 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\
252 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x)
253 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\
254 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x)
260 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\
261 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)
262 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\
263 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)
266 #define ANA_VLANTIDX_V_INDEX_SET(x)\
267 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x)
268 #define ANA_VLANTIDX_V_INDEX_GET(x)\
269 FIELD_GET(ANA_VLANTIDX_V_INDEX, x)
275 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\
276 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)
277 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\
278 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)
281 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\
282 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x)
283 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\
284 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x)
287 #define ANA_VLAN_CFG_VLAN_PCP_SET(x)\
288 FIELD_PREP(ANA_VLAN_CFG_VLAN_PCP, x)
289 #define ANA_VLAN_CFG_VLAN_PCP_GET(x)\
290 FIELD_GET(ANA_VLAN_CFG_VLAN_PCP, x)
293 #define ANA_VLAN_CFG_VLAN_DEI_SET(x)\
294 FIELD_PREP(ANA_VLAN_CFG_VLAN_DEI, x)
295 #define ANA_VLAN_CFG_VLAN_DEI_GET(x)\
296 FIELD_GET(ANA_VLAN_CFG_VLAN_DEI, x)
299 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\
300 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x)
301 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\
302 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x)
308 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\
309 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)
310 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\
311 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)
314 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\
315 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)
316 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\
317 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)
320 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\
321 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)
322 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\
323 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)
326 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\
327 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
328 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\
329 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
335 #define ANA_QOS_CFG_DP_DEFAULT_VAL_SET(x)\
336 FIELD_PREP(ANA_QOS_CFG_DP_DEFAULT_VAL, x)
337 #define ANA_QOS_CFG_DP_DEFAULT_VAL_GET(x)\
338 FIELD_GET(ANA_QOS_CFG_DP_DEFAULT_VAL, x)
341 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(x)\
342 FIELD_PREP(ANA_QOS_CFG_QOS_DEFAULT_VAL, x)
343 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_GET(x)\
344 FIELD_GET(ANA_QOS_CFG_QOS_DEFAULT_VAL, x)
347 #define ANA_QOS_CFG_QOS_DSCP_ENA_SET(x)\
348 FIELD_PREP(ANA_QOS_CFG_QOS_DSCP_ENA, x)
349 #define ANA_QOS_CFG_QOS_DSCP_ENA_GET(x)\
350 FIELD_GET(ANA_QOS_CFG_QOS_DSCP_ENA, x)
353 #define ANA_QOS_CFG_QOS_PCP_ENA_SET(x)\
354 FIELD_PREP(ANA_QOS_CFG_QOS_PCP_ENA, x)
355 #define ANA_QOS_CFG_QOS_PCP_ENA_GET(x)\
356 FIELD_GET(ANA_QOS_CFG_QOS_PCP_ENA, x)
359 #define ANA_QOS_CFG_DSCP_REWR_CFG_SET(x)\
360 FIELD_PREP(ANA_QOS_CFG_DSCP_REWR_CFG, x)
361 #define ANA_QOS_CFG_DSCP_REWR_CFG_GET(x)\
362 FIELD_GET(ANA_QOS_CFG_DSCP_REWR_CFG, x)
368 #define ANA_VCAP_CFG_S1_ENA_SET(x)\
369 FIELD_PREP(ANA_VCAP_CFG_S1_ENA, x)
370 #define ANA_VCAP_CFG_S1_ENA_GET(x)\
371 FIELD_GET(ANA_VCAP_CFG_S1_ENA, x)
377 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_SET(x)\
378 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_RT_CFG, x)
379 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_GET(x)\
380 FIELD_GET(ANA_VCAP_S1_CFG_KEY_RT_CFG, x)
383 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_SET(x)\
384 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x)
385 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_GET(x)\
386 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x)
389 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_SET(x)\
390 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x)
391 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_GET(x)\
392 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x)
395 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_SET(x)\
396 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x)
397 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_GET(x)\
398 FIELD_GET(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x)
404 #define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x)\
405 FIELD_PREP(ANA_VCAP_S2_CFG_ISDX_ENA, x)
406 #define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x)\
407 FIELD_GET(ANA_VCAP_S2_CFG_ISDX_ENA, x)
410 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x)\
411 FIELD_PREP(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x)
412 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x)\
413 FIELD_GET(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x)
416 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x)\
417 FIELD_PREP(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x)
418 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x)\
419 FIELD_GET(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x)
422 #define ANA_VCAP_S2_CFG_ENA_SET(x)\
423 FIELD_PREP(ANA_VCAP_S2_CFG_ENA, x)
424 #define ANA_VCAP_S2_CFG_ENA_GET(x)\
425 FIELD_GET(ANA_VCAP_S2_CFG_ENA, x)
428 #define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x)\
429 FIELD_PREP(ANA_VCAP_S2_CFG_SNAP_DIS, x)
430 #define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x)\
431 FIELD_GET(ANA_VCAP_S2_CFG_SNAP_DIS, x)
434 #define ANA_VCAP_S2_CFG_ARP_DIS_SET(x)\
435 FIELD_PREP(ANA_VCAP_S2_CFG_ARP_DIS, x)
436 #define ANA_VCAP_S2_CFG_ARP_DIS_GET(x)\
437 FIELD_GET(ANA_VCAP_S2_CFG_ARP_DIS, x)
440 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x)\
441 FIELD_PREP(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x)
442 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x)\
443 FIELD_GET(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x)
446 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x)\
447 FIELD_PREP(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x)
448 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x)\
449 FIELD_GET(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x)
452 #define ANA_VCAP_S2_CFG_IP6_CFG_SET(x)\
453 FIELD_PREP(ANA_VCAP_S2_CFG_IP6_CFG, x)
454 #define ANA_VCAP_S2_CFG_IP6_CFG_GET(x)\
455 FIELD_GET(ANA_VCAP_S2_CFG_IP6_CFG, x)
458 #define ANA_VCAP_S2_CFG_OAM_DIS_SET(x)\
459 FIELD_PREP(ANA_VCAP_S2_CFG_OAM_DIS, x)
460 #define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\
461 FIELD_GET(ANA_VCAP_S2_CFG_OAM_DIS, x)
467 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(x)\
468 FIELD_PREP(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x)
469 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_GET(x)\
470 FIELD_GET(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x)
473 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(x)\
474 FIELD_PREP(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x)
475 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_GET(x)\
476 FIELD_GET(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x)
482 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\
483 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)
484 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\
485 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)
488 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\
489 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)
490 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\
491 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)
494 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\
495 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)
496 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\
497 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)
500 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\
501 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
502 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\
503 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
512 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\
513 FIELD_PREP(ANA_PORT_CFG_SRC_MIRROR_ENA, x)
514 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\
515 FIELD_GET(ANA_PORT_CFG_SRC_MIRROR_ENA, x)
518 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\
519 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x)
520 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\
521 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x)
524 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\
525 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x)
526 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\
527 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x)
530 #define ANA_PORT_CFG_RECV_ENA_SET(x)\
531 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x)
532 #define ANA_PORT_CFG_RECV_ENA_GET(x)\
533 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x)
536 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\
537 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x)
538 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\
539 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x)
545 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(x)\
546 FIELD_PREP(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x)
547 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_GET(x)\
548 FIELD_GET(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x)
554 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\
555 FIELD_PREP(ANA_POL_CFG_PORT_POL_ENA, x)
556 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\
557 FIELD_GET(ANA_POL_CFG_PORT_POL_ENA, x)
560 #define ANA_POL_CFG_POL_ORDER_SET(x)\
561 FIELD_PREP(ANA_POL_CFG_POL_ORDER, x)
562 #define ANA_POL_CFG_POL_ORDER_GET(x)\
563 FIELD_GET(ANA_POL_CFG_POL_ORDER, x)
569 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\
570 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x)
571 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\
572 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x)
578 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\
579 FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x)
580 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\
581 FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x)
584 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\
585 FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x)
586 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\
587 FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x)
590 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\
591 FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x)
592 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\
593 FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x)
596 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\
597 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)
598 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\
599 FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)
602 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\
603 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)
604 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\
605 FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)
608 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\
609 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)
610 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\
611 FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)
614 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\
615 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)
616 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\
617 FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)
623 #define ANA_DSCP_CFG_DP_DSCP_VAL_SET(x)\
624 FIELD_PREP(ANA_DSCP_CFG_DP_DSCP_VAL, x)
625 #define ANA_DSCP_CFG_DP_DSCP_VAL_GET(x)\
626 FIELD_GET(ANA_DSCP_CFG_DP_DSCP_VAL, x)
629 #define ANA_DSCP_CFG_QOS_DSCP_VAL_SET(x)\
630 FIELD_PREP(ANA_DSCP_CFG_QOS_DSCP_VAL, x)
631 #define ANA_DSCP_CFG_QOS_DSCP_VAL_GET(x)\
632 FIELD_GET(ANA_DSCP_CFG_QOS_DSCP_VAL, x)
635 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\
636 FIELD_PREP(ANA_DSCP_CFG_DSCP_TRUST_ENA, x)
637 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\
638 FIELD_GET(ANA_DSCP_CFG_DSCP_TRUST_ENA, x)
641 #define ANA_DSCP_CFG_DSCP_REWR_ENA_SET(x)\
642 FIELD_PREP(ANA_DSCP_CFG_DSCP_REWR_ENA, x)
643 #define ANA_DSCP_CFG_DSCP_REWR_ENA_GET(x)\
644 FIELD_GET(ANA_DSCP_CFG_DSCP_REWR_ENA, x)
650 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\
651 FIELD_PREP(ANA_POL_PIR_CFG_PIR_RATE, x)
652 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\
653 FIELD_GET(ANA_POL_PIR_CFG_PIR_RATE, x)
656 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\
657 FIELD_PREP(ANA_POL_PIR_CFG_PIR_BURST, x)
658 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\
659 FIELD_GET(ANA_POL_PIR_CFG_PIR_BURST, x)
665 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\
666 FIELD_PREP(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x)
667 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\
668 FIELD_GET(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x)
671 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\
672 FIELD_PREP(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x)
673 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\
674 FIELD_GET(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x)
677 #define ANA_POL_MODE_IPG_SIZE_SET(x)\
678 FIELD_PREP(ANA_POL_MODE_IPG_SIZE, x)
679 #define ANA_POL_MODE_IPG_SIZE_GET(x)\
680 FIELD_GET(ANA_POL_MODE_IPG_SIZE, x)
683 #define ANA_POL_MODE_FRM_MODE_SET(x)\
684 FIELD_PREP(ANA_POL_MODE_FRM_MODE, x)
685 #define ANA_POL_MODE_FRM_MODE_GET(x)\
686 FIELD_GET(ANA_POL_MODE_FRM_MODE, x)
689 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\
690 FIELD_PREP(ANA_POL_MODE_OVERSHOOT_ENA, x)
691 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\
692 FIELD_GET(ANA_POL_MODE_OVERSHOOT_ENA, x)
698 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\
699 FIELD_PREP(ANA_POL_PIR_STATE_PIR_LVL, x)
700 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\
701 FIELD_GET(ANA_POL_PIR_STATE_PIR_LVL, x)
707 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\
708 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
709 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\
710 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
716 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\
717 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x)
718 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\
719 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x)
722 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\
723 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x)
724 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\
725 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x)
728 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\
729 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x)
730 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\
731 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x)
734 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\
735 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x)
736 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\
737 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x)
740 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\
741 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x)
742 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\
743 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x)
746 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\
747 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x)
748 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\
749 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x)
755 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\
756 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x)
757 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\
758 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x)
761 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\
762 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x)
763 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\
764 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x)
770 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
771 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
772 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
773 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
779 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
780 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
781 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
782 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
788 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\
789 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x)
790 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\
791 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x)
794 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
795 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
796 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
797 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
803 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\
804 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x)
805 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\
806 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x)
809 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\
810 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x)
811 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\
812 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x)
815 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\
816 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x)
817 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\
818 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x)
824 #define DEV_MAC_HDX_CFG_SEED_SET(x)\
825 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x)
826 #define DEV_MAC_HDX_CFG_SEED_GET(x)\
827 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x)
830 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\
831 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x)
832 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\
833 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x)
845 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\
846 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x)
847 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\
848 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x)
854 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
855 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
856 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
857 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
860 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\
861 FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
862 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\
863 FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
869 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\
870 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x)
871 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\
872 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x)
878 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
879 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
880 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
881 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
884 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
885 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
886 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
887 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
890 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\
891 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
892 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\
893 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
896 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\
897 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x)
898 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\
899 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x)
905 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\
906 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
907 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\
908 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
911 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
912 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
913 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
914 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
920 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
921 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
922 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
923 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
926 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
927 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
928 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
929 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
935 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
936 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
937 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
938 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
944 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
945 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
946 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
947 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
953 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
954 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
955 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
956 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
962 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
963 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
964 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
965 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
971 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\
972 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x)
973 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\
974 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x)
989 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
990 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
991 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
992 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
995 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
996 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
997 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
998 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
1001 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
1002 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
1003 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
1004 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
1007 #define FDMA_CH_CFG_CH_MEM_SET(x)\
1008 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
1009 #define FDMA_CH_CFG_CH_MEM_GET(x)\
1010 FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
1016 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
1017 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
1018 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
1019 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
1022 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
1023 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
1024 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
1025 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
1034 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
1035 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
1036 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
1037 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
1049 #define PTP_PIN_INTR_INTR_PTP_SET(x)\
1050 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x)
1051 #define PTP_PIN_INTR_INTR_PTP_GET(x)\
1052 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x)
1058 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\
1059 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x)
1060 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\
1061 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x)
1067 #define PTP_DOM_CFG_ENA_SET(x)\
1068 FIELD_PREP(PTP_DOM_CFG_ENA, x)
1069 #define PTP_DOM_CFG_ENA_GET(x)\
1070 FIELD_GET(PTP_DOM_CFG_ENA, x)
1073 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\
1074 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x)
1075 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\
1076 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x)
1085 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\
1086 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x)
1087 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\
1088 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x)
1091 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\
1092 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x)
1093 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\
1094 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x)
1097 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\
1098 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x)
1099 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\
1100 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x)
1103 #define PTP_PIN_CFG_PIN_DOM_SET(x)\
1104 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x)
1105 #define PTP_PIN_CFG_PIN_DOM_GET(x)\
1106 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x)
1112 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\
1113 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)
1114 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\
1115 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)
1124 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\
1125 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x)
1126 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\
1127 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x)
1133 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0))
1135 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0))
1141 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0))
1143 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0))
1149 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\
1150 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x)
1151 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\
1152 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x)
1155 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\
1156 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x)
1157 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\
1158 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x)
1161 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
1162 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x)
1163 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
1164 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x)
1167 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
1168 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
1169 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
1170 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
1173 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\
1174 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x)
1175 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\
1176 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x)
1182 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
1183 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
1184 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
1185 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
1191 #define QS_XTR_GRP_CFG_MODE_SET(x)\
1192 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
1193 #define QS_XTR_GRP_CFG_MODE_GET(x)\
1194 FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
1197 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
1198 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
1199 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
1200 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
1215 #define QS_INJ_GRP_CFG_MODE_SET(x)\
1216 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
1217 #define QS_INJ_GRP_CFG_MODE_GET(x)\
1218 FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
1221 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
1222 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
1223 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
1224 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
1233 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\
1234 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
1235 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\
1236 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
1239 #define QS_INJ_CTRL_EOF_SET(x)\
1240 FIELD_PREP(QS_INJ_CTRL_EOF, x)
1241 #define QS_INJ_CTRL_EOF_GET(x)\
1242 FIELD_GET(QS_INJ_CTRL_EOF, x)
1245 #define QS_INJ_CTRL_SOF_SET(x)\
1246 FIELD_PREP(QS_INJ_CTRL_SOF, x)
1247 #define QS_INJ_CTRL_SOF_GET(x)\
1248 FIELD_GET(QS_INJ_CTRL_SOF, x)
1251 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\
1252 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
1253 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\
1254 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
1260 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
1261 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
1262 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
1263 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
1266 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\
1267 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
1268 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\
1269 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
1275 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\
1276 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x)
1277 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\
1278 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x)
1284 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\
1285 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x)
1286 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\
1287 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x)
1290 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\
1291 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
1292 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\
1293 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
1296 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
1297 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
1298 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
1299 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
1302 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\
1303 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
1304 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\
1305 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
1308 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\
1309 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x)
1310 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\
1311 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x)
1317 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\
1318 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x)
1319 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\
1320 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x)
1332 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\
1333 FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x)
1334 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\
1335 FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x)
1338 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\
1339 FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x)
1340 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\
1341 FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x)
1347 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\
1348 FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x)
1349 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\
1350 FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x)
1353 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\
1354 FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x)
1355 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\
1356 FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x)
1359 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\
1360 FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x)
1361 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\
1362 FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x)
1365 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\
1366 FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x)
1367 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\
1368 FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x)
1373 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\
1374 FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x)
1375 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\
1376 FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x)
1382 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\
1383 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)
1384 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\
1385 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)
1388 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\
1389 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x)
1390 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\
1391 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x)
1394 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\
1395 FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)
1396 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\
1397 FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)
1400 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\
1401 FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)
1402 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\
1403 FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)
1409 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\
1410 FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x)
1411 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\
1412 FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x)
1418 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\
1419 FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x)
1420 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\
1421 FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x)
1427 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\
1428 FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)
1429 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\
1430 FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)
1433 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\
1434 FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)
1435 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\
1436 FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)
1442 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\
1443 FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x)
1444 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\
1445 FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x)
1454 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\
1455 FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)
1456 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\
1457 FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)
1466 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\
1467 FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)
1468 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\
1469 FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)
1475 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\
1476 FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)
1477 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\
1478 FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)
1484 #define QSYS_TAS_LST_LIST_STATE_SET(x)\
1485 FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x)
1486 #define QSYS_TAS_LST_LIST_STATE_GET(x)\
1487 FIELD_GET(QSYS_TAS_LST_LIST_STATE, x)
1493 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\
1494 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)
1495 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\
1496 FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)
1499 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\
1500 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)
1501 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\
1502 FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)
1505 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\
1506 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)
1507 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\
1508 FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)
1514 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\
1515 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)
1516 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\
1517 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)
1520 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\
1521 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)
1522 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\
1523 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)
1532 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\
1533 FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)
1534 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\
1535 FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)
1541 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\
1542 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x)
1543 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\
1544 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x)
1547 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
1548 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
1549 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
1550 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
1556 #define REW_TAG_CFG_TAG_CFG_SET(x)\
1557 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x)
1558 #define REW_TAG_CFG_TAG_CFG_GET(x)\
1559 FIELD_GET(REW_TAG_CFG_TAG_CFG, x)
1562 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\
1563 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x)
1564 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\
1565 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x)
1568 #define REW_TAG_CFG_TAG_PCP_CFG_SET(x)\
1569 FIELD_PREP(REW_TAG_CFG_TAG_PCP_CFG, x)
1570 #define REW_TAG_CFG_TAG_PCP_CFG_GET(x)\
1571 FIELD_GET(REW_TAG_CFG_TAG_PCP_CFG, x)
1574 #define REW_TAG_CFG_TAG_DEI_CFG_SET(x)\
1575 FIELD_PREP(REW_TAG_CFG_TAG_DEI_CFG, x)
1576 #define REW_TAG_CFG_TAG_DEI_CFG_GET(x)\
1577 FIELD_GET(REW_TAG_CFG_TAG_DEI_CFG, x)
1583 #define REW_PORT_CFG_ES0_EN_SET(x)\
1584 FIELD_PREP(REW_PORT_CFG_ES0_EN, x)
1585 #define REW_PORT_CFG_ES0_EN_GET(x)\
1586 FIELD_GET(REW_PORT_CFG_ES0_EN, x)
1589 #define REW_PORT_CFG_NO_REWRITE_SET(x)\
1590 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x)
1591 #define REW_PORT_CFG_NO_REWRITE_GET(x)\
1592 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x)
1598 #define REW_DSCP_CFG_DSCP_REWR_CFG_SET(x)\
1599 FIELD_PREP(REW_DSCP_CFG_DSCP_REWR_CFG, x)
1600 #define REW_DSCP_CFG_DSCP_REWR_CFG_GET(x)\
1601 FIELD_GET(REW_DSCP_CFG_DSCP_REWR_CFG, x)
1607 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(x)\
1608 FIELD_PREP(REW_PCP_DEI_CFG_DEI_QOS_VAL, x)
1609 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_GET(x)\
1610 FIELD_GET(REW_PCP_DEI_CFG_DEI_QOS_VAL, x)
1613 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(x)\
1614 FIELD_PREP(REW_PCP_DEI_CFG_PCP_QOS_VAL, x)
1615 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_GET(x)\
1616 FIELD_GET(REW_PCP_DEI_CFG_PCP_QOS_VAL, x)
1622 #define REW_STAT_CFG_STAT_MODE_SET(x)\
1623 FIELD_PREP(REW_STAT_CFG_STAT_MODE, x)
1624 #define REW_STAT_CFG_STAT_MODE_GET(x)\
1625 FIELD_GET(REW_STAT_CFG_STAT_MODE, x)
1631 #define SYS_RESET_CFG_CORE_ENA_SET(x)\
1632 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x)
1633 #define SYS_RESET_CFG_CORE_ENA_GET(x)\
1634 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x)
1640 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\
1641 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x)
1642 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\
1643 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x)
1646 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\
1647 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x)
1648 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\
1649 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x)
1655 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\
1656 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x)
1657 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\
1658 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x)
1664 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\
1665 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x)
1666 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\
1667 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x)
1673 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\
1674 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x)
1675 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\
1676 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x)
1682 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\
1683 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x)
1684 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\
1685 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x)
1688 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
1689 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x)
1690 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
1691 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x)
1694 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
1695 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x)
1696 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
1697 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x)
1709 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\
1710 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
1711 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\
1712 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
1715 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\
1716 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
1717 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\
1718 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
1721 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\
1722 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
1723 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\
1724 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
1727 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\
1728 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x)
1729 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\
1730 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x)
1733 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\
1734 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x)
1735 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\
1736 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x)
1739 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\
1740 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
1741 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\
1742 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
1751 #define SYS_RAM_INIT_RAM_INIT_SET(x)\
1752 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x)
1753 #define SYS_RAM_INIT_RAM_INIT_GET(x)\
1754 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x)
1760 #define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x)\
1761 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CMD, x)
1762 #define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x)\
1763 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CMD, x)
1766 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x)\
1767 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x)
1768 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x)\
1769 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x)
1772 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x)\
1773 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x)
1774 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x)\
1775 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x)
1778 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x)\
1779 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x)
1780 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x)\
1781 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x)
1784 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x)\
1785 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ADDR, x)
1786 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x)\
1787 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ADDR, x)
1790 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x)\
1791 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_SHOT, x)
1792 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x)\
1793 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_SHOT, x)
1796 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x)\
1797 FIELD_PREP(VCAP_UPDATE_CTRL_CLEAR_CACHE, x)
1798 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x)\
1799 FIELD_GET(VCAP_UPDATE_CTRL_CLEAR_CACHE, x)
1802 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x)\
1803 FIELD_PREP(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x)
1804 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x)\
1805 FIELD_GET(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x)
1811 #define VCAP_MV_CFG_MV_NUM_POS_SET(x)\
1812 FIELD_PREP(VCAP_MV_CFG_MV_NUM_POS, x)
1813 #define VCAP_MV_CFG_MV_NUM_POS_GET(x)\
1814 FIELD_GET(VCAP_MV_CFG_MV_NUM_POS, x)
1817 #define VCAP_MV_CFG_MV_SIZE_SET(x)\
1818 FIELD_PREP(VCAP_MV_CFG_MV_SIZE, x)
1819 #define VCAP_MV_CFG_MV_SIZE_GET(x)\
1820 FIELD_GET(VCAP_MV_CFG_MV_SIZE, x)
1844 #define VCAP_CORE_IDX_CORE_IDX_SET(x)\
1845 FIELD_PREP(VCAP_CORE_IDX_CORE_IDX, x)
1846 #define VCAP_CORE_IDX_CORE_IDX_GET(x)\
1847 FIELD_GET(VCAP_CORE_IDX_CORE_IDX, x)
1853 #define VCAP_CORE_MAP_CORE_MAP_SET(x)\
1854 FIELD_PREP(VCAP_CORE_MAP_CORE_MAP, x)
1855 #define VCAP_CORE_MAP_CORE_MAP_GET(x)\
1856 FIELD_GET(VCAP_CORE_MAP_CORE_MAP, x)