Lines Matching defs:priv

71 static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
74 	struct net_device *dev = priv->ndev;
98 static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
100 	struct net_device *dev = priv->ndev;
102 	int ret = regmap_read(priv->ctx.regmap, reg, &val);
105 		netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
110 static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
112 	struct net_device *dev = priv->ndev;
113 	int ret = regmap_write(priv->ctx.regmap, reg, val);
116 		netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
120 static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
123 	struct net_device *dev = priv->ndev;
124 	int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
127 		netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
131 static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
133 	struct net_device *dev = priv->ndev;
135 	int ret = regmap_read(priv->ctx.phymap, reg, &val);
138 		netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
143 static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
145 	struct net_device *dev = priv->ndev;
146 	int ret = regmap_write(priv->ctx.phymap, reg, val);
149 		netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
153 static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
155 	encx24j600_update_reg(priv, reg, mask, 0);
158 static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
160 	encx24j600_update_reg(priv, reg, mask, mask);
163 static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
165 	struct net_device *dev = priv->ndev;
166 	int ret = regmap_write(priv->ctx.regmap, cmd, 0);
169 		netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
173 static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
178 	mutex_lock(&priv->ctx.mutex);
179 	ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
180 	mutex_unlock(&priv->ctx.mutex);
185 static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
190 	mutex_lock(&priv->ctx.mutex);
191 	ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
192 	mutex_unlock(&priv->ctx.mutex);
197 static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
199 	u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
201 	if (priv->autoneg == AUTONEG_ENABLE) {
205 		if (priv->speed == SPEED_100)
210 		if (priv->full_duplex)
215 	encx24j600_write_phy(priv, PHCON1, phcon1);
219 static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
221 	struct net_device *dev = priv->ndev;
226 	phstat1 = encx24j600_read_phy(priv, PHSTAT1);
231 			netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
233 			priv->autoneg = AUTONEG_DISABLE;
234 			phstat3 = encx24j600_read_phy(priv, PHSTAT3);
235 			priv->speed = (phstat3 & PHY3SPD100)
237 			priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
238 			encx24j600_update_phcon1(priv);
239 			netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
240 				     priv->speed == SPEED_100 ? "100" : "10",
241 				     priv->full_duplex ? "Full" : "Half");
246 		phstat1 = encx24j600_read_phy(priv, PHSTAT1);
249 	estat = encx24j600_read_reg(priv, ESTAT);
251 		encx24j600_set_bits(priv, MACON2, FULDPX);
252 		encx24j600_write_reg(priv, MABBIPG, 0x15);
254 		encx24j600_clr_bits(priv, MACON2, FULDPX);
255 		encx24j600_write_reg(priv, MABBIPG, 0x12);
257 		encx24j600_write_reg(priv, MACLCON, 0x370f);
264 static void encx24j600_check_link_status(struct encx24j600_priv *priv)
266 	struct net_device *dev = priv->ndev;
269 	estat = encx24j600_read_reg(priv, ESTAT);
272 		if (priv->autoneg == AUTONEG_ENABLE)
273 			encx24j600_wait_for_autoneg(priv);
276 		netif_info(priv, ifup, dev, "link up\n");
278 		netif_info(priv, ifdown, dev, "link down\n");
283 		priv->autoneg  = AUTONEG_ENABLE;
284 		priv->full_duplex = true;
285 		priv->speed = SPEED_100;
290 static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
292 	struct net_device *dev = priv->ndev;
294 	netif_dbg(priv, intr, dev, "%s", __func__);
295 	encx24j600_check_link_status(priv);
296 	encx24j600_clr_bits(priv, EIR, LINKIF);
299 static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
301 	struct net_device *dev = priv->ndev;
303 	if (!priv->tx_skb) {
308 	mutex_lock(&priv->lock);
315 	dev->stats.tx_bytes += priv->tx_skb->len;
317 	encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
319 	netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
321 	dev_kfree_skb(priv->tx_skb);
322 	priv->tx_skb = NULL;
326 	mutex_unlock(&priv->lock);
329 static int encx24j600_receive_packet(struct encx24j600_priv *priv,
332 	struct net_device *dev = priv->ndev;
341 	encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
343 	if (netif_msg_pktdata(priv))
359 static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
361 	struct net_device *dev = priv->ndev;
367 		encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
368 		encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
370 		if (netif_msg_rx_status(priv))
371 			encx24j600_dump_rsv(priv, __func__, &rsv);
375 			netif_err(priv, rx_err, dev, "RX Error %04x\n",
386 			encx24j600_receive_packet(priv, &rsv);
389 		priv->next_packet = rsv.next_packet;
391 		newrxtail = priv->next_packet - 2;
395 		encx24j600_cmd(priv, SETPKTDEC);
396 		encx24j600_write_reg(priv, ERXTAIL, newrxtail);
402 	struct encx24j600_priv *priv = dev_id;
403 	struct net_device *dev = priv->ndev;
407 	encx24j600_cmd(priv, CLREIE);
409 	eir = encx24j600_read_reg(priv, EIR);
412 		encx24j600_int_link_handler(priv);
415 		encx24j600_tx_complete(priv, false);
418 		encx24j600_tx_complete(priv, true);
423 			netif_err(priv, rx_err, dev, "Packet counter full\n");
426 		encx24j600_clr_bits(priv, EIR, RXABTIF);
432 		mutex_lock(&priv->lock);
434 		packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
436 			encx24j600_rx_packets(priv, packet_count);
437 			packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
440 		mutex_unlock(&priv->lock);
444 	encx24j600_cmd(priv, SETEIE);
449 static int encx24j600_soft_reset(struct encx24j600_priv *priv)
456 	regcache_cache_bypass(priv->ctx.regmap, true);
459 		encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
460 		eudast = encx24j600_read_reg(priv, EUDAST);
463 	regcache_cache_bypass(priv->ctx.regmap, false);
472 	while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
481 	encx24j600_cmd(priv, SETETHRST);
485 	if (encx24j600_read_reg(priv, EUDAST) != 0) {
497 static int encx24j600_hw_reset(struct encx24j600_priv *priv)
501 	mutex_lock(&priv->lock);
502 	ret = encx24j600_soft_reset(priv);
503 	mutex_unlock(&priv->lock);
508 static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
510 	encx24j600_set_bits(priv, ECON2, TXRST);
511 	encx24j600_clr_bits(priv, ECON2, TXRST);
514 static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
517 	encx24j600_reset_hw_tx(priv);
520 	encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
523 	encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
526 static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
528 	encx24j600_cmd(priv, DISABLERX);
531 	encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
534 	encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
536 	priv->next_packet = ENC_RX_BUF_START;
539 	encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
542 	encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
543 	encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
546 	encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
549 static void encx24j600_dump_config(struct encx24j600_priv *priv,
555 	pr_info(DRV_NAME " ECON1:   %04X\n", encx24j600_read_reg(priv, ECON1));
556 	pr_info(DRV_NAME " ECON2:   %04X\n", encx24j600_read_reg(priv, ECON2));
557 	pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
559 	pr_info(DRV_NAME " ESTAT:   %04X\n", encx24j600_read_reg(priv, ESTAT));
560 	pr_info(DRV_NAME " EIR:     %04X\n", encx24j600_read_reg(priv, EIR));
561 	pr_info(DRV_NAME " EIDLED:  %04X\n", encx24j600_read_reg(priv, EIDLED));
564 	pr_info(DRV_NAME " MACON1:  %04X\n", encx24j600_read_reg(priv, MACON1));
565 	pr_info(DRV_NAME " MACON2:  %04X\n", encx24j600_read_reg(priv, MACON2));
566 	pr_info(DRV_NAME " MAIPG:   %04X\n", encx24j600_read_reg(priv, MAIPG));
567 	pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
569 	pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
573 	pr_info(DRV_NAME " PHCON1:  %04X\n", encx24j600_read_phy(priv, PHCON1));
574 	pr_info(DRV_NAME " PHCON2:  %04X\n", encx24j600_read_phy(priv, PHCON2));
575 	pr_info(DRV_NAME " PHANA:   %04X\n", encx24j600_read_phy(priv, PHANA));
576 	pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
578 	pr_info(DRV_NAME " PHANE:   %04X\n", encx24j600_read_phy(priv, PHANE));
579 	pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
581 	pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
583 	pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
587 static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
589 	switch (priv->rxfilter) {
591 		encx24j600_set_bits(priv, MACON1, PASSALL);
592 		encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
595 		encx24j600_clr_bits(priv, MACON1, PASSALL);
596 		encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
600 		encx24j600_clr_bits(priv, MACON1, PASSALL);
601 		encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
606 static void encx24j600_hw_init(struct encx24j600_priv *priv)
610 	priv->hw_enabled = false;
616 	encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00);
619 	encx24j600_write_reg(priv, MACON1, 0x9);
622 	encx24j600_write_reg(priv, MAIPG, 0x0c12);
625 	encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
627 	encx24j600_update_phcon1(priv);
628 	encx24j600_check_link_status(priv);
631 	if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
634 	encx24j600_set_bits(priv, MACON2, macon2);
636 	priv->rxfilter = RXFILTER_NORMAL;
637 	encx24j600_set_rxfilter_mode(priv);
640 	encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
643 	encx24j600_hw_init_tx(priv);
646 	encx24j600_hw_init_rx(priv);
648 	if (netif_msg_hw(priv))
649 		encx24j600_dump_config(priv, "Hw is initialized");
652 static void encx24j600_hw_enable(struct encx24j600_priv *priv)
655 	encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
659 	encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
663 	encx24j600_cmd(priv, ENABLERX);
665 	priv->hw_enabled = true;
668 static void encx24j600_hw_disable(struct encx24j600_priv *priv)
671 	encx24j600_write_reg(priv, EIE, 0);
674 	encx24j600_cmd(priv, DISABLERX);
676 	priv->hw_enabled = false;
682 	struct encx24j600_priv *priv = netdev_priv(dev);
685 	if (!priv->hw_enabled) {
690 			priv->autoneg = (autoneg == AUTONEG_ENABLE);
691 			priv->full_duplex = (duplex == DUPLEX_FULL);
692 			priv->speed = (speed == SPEED_100);
694 			netif_warn(priv, link, dev, "unsupported link speed setting\n");
700 		netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
706 static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
711 	val = encx24j600_read_reg(priv, MAADR1);
716 	val = encx24j600_read_reg(priv, MAADR2);
721 	val = encx24j600_read_reg(priv, MAADR3);
730 	struct encx24j600_priv *priv = netdev_priv(dev);
732 	if (priv->hw_enabled) {
733 		netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
737 	mutex_lock(&priv->lock);
739 	netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
742 	encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
744 	encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
746 	encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
749 	mutex_unlock(&priv->lock);
770 	struct encx24j600_priv *priv = netdev_priv(dev);
772 	int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
774 				       DRV_NAME, priv);
777 			   priv->ctx.spi->irq, ret);
781 	encx24j600_hw_disable(priv);
782 	encx24j600_hw_init(priv);
783 	encx24j600_hw_enable(priv);
791 	struct encx24j600_priv *priv = netdev_priv(dev);
794 	free_irq(priv->ctx.spi->irq, priv);
800 	struct encx24j600_priv *priv =
803 	mutex_lock(&priv->lock);
804 	encx24j600_set_rxfilter_mode(priv);
805 	mutex_unlock(&priv->lock);
810 	struct encx24j600_priv *priv = netdev_priv(dev);
811 	int oldfilter = priv->rxfilter;
814 		netif_dbg(priv, link, dev, "promiscuous mode\n");
815 		priv->rxfilter = RXFILTER_PROMISC;
817 		netif_dbg(priv, link, dev, "%smulticast mode\n",
819 		priv->rxfilter = RXFILTER_MULTI;
821 		netif_dbg(priv, link, dev, "normal mode\n");
822 		priv->rxfilter = RXFILTER_NORMAL;
825 	if (oldfilter != priv->rxfilter)
826 		kthread_queue_work(&priv->kworker, &priv->setrx_work);
829 static void encx24j600_hw_tx(struct encx24j600_priv *priv)
831 	struct net_device *dev = priv->ndev;
833 	netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
834 		   priv->tx_skb->len);
836 	if (netif_msg_pktdata(priv))
837 		dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
839 	if (encx24j600_read_reg(priv, EIR) & TXABTIF)
843 		encx24j600_reset_hw_tx(priv);
846 	encx24j600_clr_bits(priv, EIR, TXIF);
849 	encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
852 	encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
853 			     priv->tx_skb->len);
856 	encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
859 	encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
862 	encx24j600_cmd(priv, SETTXRTS);
867 	struct encx24j600_priv *priv =
870 	mutex_lock(&priv->lock);
871 	encx24j600_hw_tx(priv);
872 	mutex_unlock(&priv->lock);
877 	struct encx24j600_priv *priv = netdev_priv(dev);
885 	priv->tx_skb = skb;
887 	kthread_queue_work(&priv->kworker, &priv->tx_work);
895 	struct encx24j600_priv *priv = netdev_priv(dev);
897 	netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
912 	struct encx24j600_priv *priv = netdev_priv(dev);
917 	mutex_lock(&priv->lock);
921 		regmap_read(priv->ctx.regmap, reg, &val);
924 	mutex_unlock(&priv->lock);
939 	struct encx24j600_priv *priv = netdev_priv(dev);
949 	cmd->base.speed = priv->speed;
950 	cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
952 	cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
967 	struct encx24j600_priv *priv = netdev_priv(dev);
969 	return priv->msg_enable;
974 	struct encx24j600_priv *priv = netdev_priv(dev);
976 	priv->msg_enable = val;
1004 	struct encx24j600_priv *priv;
1015 	priv = netdev_priv(ndev);
1016 	spi_set_drvdata(spi, priv);
1017 	dev_set_drvdata(&spi->dev, priv);
1020 	priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1021 	priv->ndev = ndev;
1024 	priv->full_duplex = true;
1025 	priv->autoneg = AUTONEG_ENABLE;
1026 	priv->speed = SPEED_100;
1028 	priv->ctx.spi = spi;
1032 	ret = devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
1036 	mutex_init(&priv->lock);
1039 	if (encx24j600_hw_reset(priv)) {
1040 		netif_err(priv, probe, ndev,
1047 	encx24j600_hw_init(priv);
1049 	kthread_init_worker(&priv->kworker);
1050 	kthread_init_work(&priv->tx_work, encx24j600_tx_proc);
1051 	kthread_init_work(&priv->setrx_work, encx24j600_setrx_proc);
1053 	priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
1056 	if (IS_ERR(priv->kworker_task)) {
1057 		ret = PTR_ERR(priv->kworker_task);
1062 	encx24j600_hw_get_macaddr(priv, addr);
1069 		netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
1074 	eidled = encx24j600_read_reg(priv, EIDLED);
1080 	netif_info(priv, probe, ndev, "Silicon rev ID: 0x%02x\n",
1083 	netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
1088 	unregister_netdev(priv->ndev);
1090 	kthread_stop(priv->kworker_task);
1100 	struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
1102 	unregister_netdev(priv->ndev);
1103 	kthread_stop(priv->kworker_task);
1105 	free_netdev(priv->ndev);