Lines Matching refs:ECON1
198 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
201 if (addr >= EIE && addr <= ECON1)
207 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
210 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
215 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
218 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
534 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
544 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
635 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
637 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
660 /* Clear ECON1 */
661 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
761 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
771 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
921 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
922 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
923 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
926 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
1085 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1180 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1186 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1187 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1197 locked_reg_bfset(priv, ECON1,
1278 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);