Lines Matching defs:priv

84 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
86 	struct device *dev = &priv->spi->dev;
87 	u8 *rx_buf = priv->spi_transfer_buf + 4;
88 	u8 *tx_buf = priv->spi_transfer_buf;
106 	ret = spi_sync(priv->spi, &msg);
111 	if (ret && netif_msg_drv(priv))
121 static int spi_write_buf(struct enc28j60_net *priv, int len, const u8 *data)
123 	struct device *dev = &priv->spi->dev;
129 		priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130 		memcpy(&priv->spi_transfer_buf[1], data, len);
131 		ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132 		if (ret && netif_msg_drv(priv))
142 static u8 spi_read_op(struct enc28j60_net *priv, u8 op, u8 addr)
144 	struct device *dev = &priv->spi->dev;
156 	ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
169 static int spi_write_op(struct enc28j60_net *priv, u8 op, u8 addr, u8 val)
171 	struct device *dev = &priv->spi->dev;
174 	priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175 	priv->spi_transfer_buf[1] = val;
176 	ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177 	if (ret && netif_msg_drv(priv))
183 static void enc28j60_soft_reset(struct enc28j60_net *priv)
185 	spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
194 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
205 	if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
207 			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
210 			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
213 	if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
215 			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
218 			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
221 	priv->bank = b;
238 static void nolock_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
240 	enc28j60_set_bank(priv, addr);
241 	spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
244 static void locked_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
246 	mutex_lock(&priv->lock);
247 	nolock_reg_bfset(priv, addr, mask);
248 	mutex_unlock(&priv->lock);
254 static void nolock_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
256 	enc28j60_set_bank(priv, addr);
257 	spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
260 static void locked_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
262 	mutex_lock(&priv->lock);
263 	nolock_reg_bfclr(priv, addr, mask);
264 	mutex_unlock(&priv->lock);
270 static int nolock_regb_read(struct enc28j60_net *priv, u8 address)
272 	enc28j60_set_bank(priv, address);
273 	return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
276 static int locked_regb_read(struct enc28j60_net *priv, u8 address)
280 	mutex_lock(&priv->lock);
281 	ret = nolock_regb_read(priv, address);
282 	mutex_unlock(&priv->lock);
290 static int nolock_regw_read(struct enc28j60_net *priv, u8 address)
294 	enc28j60_set_bank(priv, address);
295 	rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
296 	rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
301 static int locked_regw_read(struct enc28j60_net *priv, u8 address)
305 	mutex_lock(&priv->lock);
306 	ret = nolock_regw_read(priv, address);
307 	mutex_unlock(&priv->lock);
315 static void nolock_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
317 	enc28j60_set_bank(priv, address);
318 	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
321 static void locked_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
323 	mutex_lock(&priv->lock);
324 	nolock_regb_write(priv, address, data);
325 	mutex_unlock(&priv->lock);
331 static void nolock_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
333 	enc28j60_set_bank(priv, address);
334 	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
335 	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
339 static void locked_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
341 	mutex_lock(&priv->lock);
342 	nolock_regw_write(priv, address, data);
343 	mutex_unlock(&priv->lock);
350 static void enc28j60_mem_read(struct enc28j60_net *priv, u16 addr, int len,
353 	mutex_lock(&priv->lock);
354 	nolock_regw_write(priv, ERDPTL, addr);
356 	if (netif_msg_drv(priv)) {
357 		struct device *dev = &priv->spi->dev;
360 		reg = nolock_regw_read(priv, ERDPTL);
367 	spi_read_buf(priv, len, data);
368 	mutex_unlock(&priv->lock);
375 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
377 	struct device *dev = &priv->spi->dev;
379 	mutex_lock(&priv->lock);
381 	nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
383 	if (netif_msg_drv(priv)) {
385 		reg = nolock_regw_read(priv, EWRPTL);
393 	nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
395 	spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
396 	if (netif_msg_hw(priv))
399 			   __func__, nolock_regw_read(priv, EWRPTL));
401 	spi_write_buf(priv, len, data);
402 	if (netif_msg_hw(priv))
405 			   __func__, nolock_regw_read(priv, EWRPTL), len);
406 	mutex_unlock(&priv->lock);
409 static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
411 	struct device *dev = &priv->spi->dev;
415 	while ((nolock_regb_read(priv, reg) & mask) != val) {
417 			if (netif_msg_drv(priv))
429 static int wait_phy_ready(struct enc28j60_net *priv)
431 	return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
438 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
442 	mutex_lock(&priv->lock);
444 	nolock_regb_write(priv, MIREGADR, address);
446 	nolock_regb_write(priv, MICMD, MICMD_MIIRD);
448 	wait_phy_ready(priv);
450 	nolock_regb_write(priv, MICMD, 0x00);
452 	ret = nolock_regw_read(priv, MIRDL);
453 	mutex_unlock(&priv->lock);
458 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
462 	mutex_lock(&priv->lock);
464 	nolock_regb_write(priv, MIREGADR, address);
466 	nolock_regw_write(priv, MIWRL, data);
468 	ret = wait_phy_ready(priv);
469 	mutex_unlock(&priv->lock);
480 	struct enc28j60_net *priv = netdev_priv(ndev);
481 	struct device *dev = &priv->spi->dev;
483 	mutex_lock(&priv->lock);
484 	if (!priv->hw_enable) {
485 		if (netif_msg_drv(priv))
489 		nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
490 		nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
491 		nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
492 		nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
493 		nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
494 		nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
497 		if (netif_msg_drv(priv))
503 	mutex_unlock(&priv->lock);
526 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
528 	struct device *dev = &priv->spi->dev;
530 	mutex_lock(&priv->lock);
543 		   msg, nolock_regb_read(priv, EREVID),
544 		   nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
545 		   nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
546 		   nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
547 		   nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
548 		   nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
549 		   nolock_regw_read(priv, ERXWRPTL),
550 		   nolock_regw_read(priv, ERXRDPTL),
551 		   nolock_regb_read(priv, ERXFCON),
552 		   nolock_regb_read(priv, EPKTCNT),
553 		   nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
554 		   nolock_regw_read(priv, ETXNDL),
555 		   nolock_regb_read(priv, MACLCON1),
556 		   nolock_regb_read(priv, MACLCON2),
557 		   nolock_regb_read(priv, MAPHSUP));
558 	mutex_unlock(&priv->lock);
587 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
589 	struct device *dev = &priv->spi->dev;
593 		if (netif_msg_drv(priv))
599 	priv->next_pk_ptr = start;
600 	nolock_regw_write(priv, ERXSTL, start);
601 	erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
602 	nolock_regw_write(priv, ERXRDPTL, erxrdpt);
603 	nolock_regw_write(priv, ERXNDL, end);
606 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
608 	struct device *dev = &priv->spi->dev;
611 		if (netif_msg_drv(priv))
617 	nolock_regw_write(priv, ETXSTL, start);
618 	nolock_regw_write(priv, ETXNDL, end);
626 static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
628 	struct device *dev = &priv->spi->dev;
630 	if (netif_msg_drv(priv))
633 	mutex_lock(&priv->lock);
635 		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
636 		poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
637 		poll_ready(priv, ECON1, ECON1_TXRTS, 0);
639 		nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
641 		nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
642 		poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
645 	mutex_unlock(&priv->lock);
648 static int enc28j60_hw_init(struct enc28j60_net *priv)
650 	struct device *dev = &priv->spi->dev;
653 	if (netif_msg_drv(priv))
655 			   priv->full_duplex ? "FullDuplex" : "HalfDuplex");
657 	mutex_lock(&priv->lock);
659 	enc28j60_soft_reset(priv);
661 	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
662 	priv->bank = 0;
663 	priv->hw_enable = false;
664 	priv->tx_retry_count = 0;
665 	priv->max_pk_counter = 0;
666 	priv->rxfilter = RXFILTER_NORMAL;
668 	nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
670 	nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
671 	nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
672 	mutex_unlock(&priv->lock);
679 	reg = locked_regb_read(priv, EREVID);
680 	if (netif_msg_drv(priv))
683 		if (netif_msg_drv(priv))
690 	locked_regb_write(priv, ERXFCON,
694 	locked_regb_write(priv, MACON1,
697 	if (priv->full_duplex) {
698 		locked_regb_write(priv, MACON3,
702 		locked_regb_write(priv, MAIPGL, 0x12);
704 		locked_regb_write(priv, MABBIPG, 0x15);
706 		locked_regb_write(priv, MACON3,
709 		locked_regb_write(priv, MACON4, 1 << 6);	/* DEFER bit */
711 		locked_regw_write(priv, MAIPGL, 0x0C12);
713 		locked_regb_write(priv, MABBIPG, 0x12);
720 	locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
723 	if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
726 	if (priv->full_duplex) {
727 		if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
729 		if (!enc28j60_phy_write(priv, PHCON2, 0x00))
732 		if (!enc28j60_phy_write(priv, PHCON1, 0x00))
734 		if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
737 	if (netif_msg_hw(priv))
738 		enc28j60_dump_regs(priv, "Hw initialized.");
743 static void enc28j60_hw_enable(struct enc28j60_net *priv)
745 	struct device *dev = &priv->spi->dev;
748 	if (netif_msg_hw(priv))
752 	enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
754 	mutex_lock(&priv->lock);
755 	nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
757 	nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
761 	nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
762 	priv->hw_enable = true;
763 	mutex_unlock(&priv->lock);
766 static void enc28j60_hw_disable(struct enc28j60_net *priv)
768 	mutex_lock(&priv->lock);
770 	nolock_regb_write(priv, EIE, 0x00);
771 	nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
772 	priv->hw_enable = false;
773 	mutex_unlock(&priv->lock);
779 	struct enc28j60_net *priv = netdev_priv(ndev);
782 	if (!priv->hw_enable) {
787 			priv->full_duplex = (duplex == DUPLEX_FULL);
789 			if (netif_msg_link(priv))
794 		if (netif_msg_link(priv))
804 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
806 	struct device *dev = &priv->spi->dev;
809 	endptr = locked_regw_read(priv, ETXNDL);
810 	if (netif_msg_hw(priv))
813 	enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
816 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
819 	struct device *dev = &priv->spi->dev;
862 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
865 	struct device *dev = &priv->spi->dev;
904 	struct enc28j60_net *priv = netdev_priv(ndev);
905 	struct device *dev = &priv->spi->dev;
911 	if (netif_msg_rx_status(priv))
913 			      priv->next_pk_ptr);
915 	if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
916 		if (netif_msg_rx_err(priv))
918 				   __func__, priv->next_pk_ptr);
920 		mutex_lock(&priv->lock);
921 		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
922 		nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
923 		nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
924 		nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
925 		nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
926 		nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
927 		mutex_unlock(&priv->lock);
932 	enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
946 	if (netif_msg_rx_status(priv))
947 		enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
950 		if (netif_msg_rx_err(priv))
962 			if (netif_msg_rx_err(priv))
968 			enc28j60_mem_read(priv,
969 				rx_packet_start(priv->next_pk_ptr),
971 			if (netif_msg_pktdata(priv))
986 	if (netif_msg_hw(priv))
990 	mutex_lock(&priv->lock);
991 	nolock_regw_write(priv, ERXRDPTL, erxrdpt);
993 	if (netif_msg_drv(priv)) {
995 		reg = nolock_regw_read(priv, ERXRDPTL);
1002 	priv->next_pk_ptr = next_packet;
1004 	nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1005 	mutex_unlock(&priv->lock);
1011 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1013 	struct net_device *ndev = priv->netdev;
1017 	mutex_lock(&priv->lock);
1018 	epkcnt = nolock_regb_read(priv, EPKTCNT);
1022 		erxst = nolock_regw_read(priv, ERXSTL);
1023 		erxnd = nolock_regw_read(priv, ERXNDL);
1024 		erxwr = nolock_regw_read(priv, ERXWRPTL);
1025 		erxrd = nolock_regw_read(priv, ERXRDPTL);
1034 	mutex_unlock(&priv->lock);
1035 	if (netif_msg_rx_status(priv))
1046 	struct enc28j60_net *priv = netdev_priv(ndev);
1047 	struct device *dev = &priv->spi->dev;
1051 	reg = enc28j60_phy_read(priv, PHSTAT2);
1052 	if (netif_msg_hw(priv))
1055 			   enc28j60_phy_read(priv, PHSTAT1), reg);
1060 		if (netif_msg_ifup(priv))
1064 		if (netif_msg_ifdown(priv))
1072 	struct enc28j60_net *priv = netdev_priv(ndev);
1079 	if (priv->tx_skb) {
1081 			ndev->stats.tx_bytes += priv->tx_skb->len;
1082 		dev_kfree_skb(priv->tx_skb);
1083 		priv->tx_skb = NULL;
1085 	locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1099 	struct enc28j60_net *priv = netdev_priv(ndev);
1102 	pk_counter = locked_regb_read(priv, EPKTCNT);
1103 	if (pk_counter && netif_msg_intr(priv))
1106 	if (pk_counter > priv->max_pk_counter) {
1108 		priv->max_pk_counter = pk_counter;
1109 		if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1111 				      priv->max_pk_counter);
1122 	struct enc28j60_net *priv = dev_id;
1123 	struct net_device *ndev = priv->netdev;
1127 	locked_reg_bfclr(priv, EIE, EIE_INTIE);
1131 		intflags = locked_regb_read(priv, EIR);
1135 			if (netif_msg_intr(priv))
1138 			locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1143 			if (netif_msg_intr(priv))
1148 			enc28j60_phy_read(priv, PHIR);
1155 			if (netif_msg_intr(priv))
1158 			priv->tx_retry_count = 0;
1159 			if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1160 				if (netif_msg_tx_err(priv))
1164 			if (netif_msg_tx_done(priv)) {
1166 				enc28j60_read_tsv(priv, tsv);
1167 				enc28j60_dump_tsv(priv, "Tx Done", tsv);
1170 			locked_reg_bfclr(priv, EIR, EIR_TXIF);
1177 			if (netif_msg_intr(priv))
1180 			locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1181 			enc28j60_read_tsv(priv, tsv);
1182 			if (netif_msg_tx_err(priv))
1183 				enc28j60_dump_tsv(priv, "Tx Error", tsv);
1185 			mutex_lock(&priv->lock);
1186 			nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1187 			nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1188 			nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1189 			mutex_unlock(&priv->lock);
1192 				if (netif_msg_tx_err(priv))
1195 						      priv->tx_retry_count);
1196 				if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1197 					locked_reg_bfset(priv, ECON1,
1203 			locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
1208 			if (netif_msg_intr(priv))
1212 			if (enc28j60_get_free_rxfifo(priv) <= 0) {
1213 				if (netif_msg_rx_err(priv))
1217 			locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1225 	locked_reg_bfset(priv, EIE, EIE_INTIE);
1235 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1237 	struct net_device *ndev = priv->netdev;
1239 	BUG_ON(!priv->tx_skb);
1241 	if (netif_msg_tx_queued(priv))
1243 			      priv->tx_skb->len);
1245 	if (netif_msg_pktdata(priv))
1247 			    priv->tx_skb->len, priv->tx_skb->data);
1248 	enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1252 	if (netif_msg_drv(priv)) {
1253 		struct device *dev = &priv->spi->dev;
1258 		test_len = priv->tx_skb->len;
1263 		enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1266 			if (priv->tx_skb->data[k] != test_buf[k]) {
1269 					   k, priv->tx_skb->data[k], test_buf[k]);
1278 	locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1284 	struct enc28j60_net *priv = netdev_priv(dev);
1297 	priv->tx_skb = skb;
1298 	schedule_work(&priv->tx_work);
1305 	struct enc28j60_net *priv =
1309 	enc28j60_hw_tx(priv);
1314 	struct enc28j60_net *priv = netdev_priv(ndev);
1316 	if (netif_msg_timer(priv))
1321 	schedule_work(&priv->restart_work);
1334 	struct enc28j60_net *priv = netdev_priv(dev);
1337 		if (netif_msg_ifup(priv))
1342 	enc28j60_lowpower(priv, false);
1343 	enc28j60_hw_disable(priv);
1344 	if (!enc28j60_hw_init(priv)) {
1345 		if (netif_msg_ifup(priv))
1352 	enc28j60_hw_enable(priv);
1366 	struct enc28j60_net *priv = netdev_priv(dev);
1368 	enc28j60_hw_disable(priv);
1369 	enc28j60_lowpower(priv, true);
1383 	struct enc28j60_net *priv = netdev_priv(dev);
1384 	int oldfilter = priv->rxfilter;
1387 		if (netif_msg_link(priv))
1389 		priv->rxfilter = RXFILTER_PROMISC;
1391 		if (netif_msg_link(priv))
1394 		priv->rxfilter = RXFILTER_MULTI;
1396 		if (netif_msg_link(priv))
1398 		priv->rxfilter = RXFILTER_NORMAL;
1401 	if (oldfilter != priv->rxfilter)
1402 		schedule_work(&priv->setrx_work);
1407 	struct enc28j60_net *priv =
1409 	struct device *dev = &priv->spi->dev;
1411 	if (priv->rxfilter == RXFILTER_PROMISC) {
1412 		if (netif_msg_drv(priv))
1414 		locked_regb_write(priv, ERXFCON, 0x00);
1415 	} else if (priv->rxfilter == RXFILTER_MULTI) {
1416 		if (netif_msg_drv(priv))
1418 		locked_regb_write(priv, ERXFCON,
1422 		if (netif_msg_drv(priv))
1424 		locked_regb_write(priv, ERXFCON,
1432 	struct enc28j60_net *priv =
1434 	struct net_device *ndev = priv->netdev;
1464 	struct enc28j60_net *priv = netdev_priv(dev);
1472 	cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1489 	struct enc28j60_net *priv = netdev_priv(dev);
1490 	return priv->msg_enable;
1495 	struct enc28j60_net *priv = netdev_priv(dev);
1496 	priv->msg_enable = val;
1509 	struct enc28j60_net *priv = netdev_priv(dev);
1511 	return enc28j60_hw_init(priv);
1527 	struct enc28j60_net *priv;
1538 	priv = netdev_priv(dev);
1540 	priv->netdev = dev;	/* priv to netdev reference */
1541 	priv->spi = spi;	/* priv to spi reference */
1542 	priv->msg_enable = netif_msg_init(debug.msg_enable, ENC28J60_MSG_DEFAULT);
1543 	mutex_init(&priv->lock);
1544 	INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1545 	INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1546 	INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1547 	spi_set_drvdata(spi, priv);	/* spi to priv reference */
1551 		if (netif_msg_probe(priv))
1565 				   DRV_NAME, priv);
1567 		if (netif_msg_probe(priv))
1579 	enc28j60_lowpower(priv, true);
1583 		if (netif_msg_probe(priv))
1592 	free_irq(spi->irq, priv);
1601 	struct enc28j60_net *priv = spi_get_drvdata(spi);
1603 	unregister_netdev(priv->netdev);
1604 	free_irq(spi->irq, priv);
1605 	free_netdev(priv->netdev);