Lines Matching defs:hw_qcn
542 struct mlx4_congestion_control_mb_prio_802_1_qau_params *hw_qcn;
554 hw_qcn =
573 be32_to_cpu(hw_qcn->extended_enable) >> RPG_ENABLE_BIT;
575 be32_to_cpu(hw_qcn->rppp_max_rps);
577 be32_to_cpu(hw_qcn->rpg_time_reset);
579 be32_to_cpu(hw_qcn->rpg_byte_reset);
581 be32_to_cpu(hw_qcn->rpg_threshold);
583 be32_to_cpu(hw_qcn->rpg_max_rate);
585 be32_to_cpu(hw_qcn->rpg_ai_rate);
587 be32_to_cpu(hw_qcn->rpg_hai_rate);
589 be32_to_cpu(hw_qcn->rpg_gd);
591 be32_to_cpu(hw_qcn->rpg_min_dec_fac);
593 be32_to_cpu(hw_qcn->rpg_min_rate);
605 struct mlx4_congestion_control_mb_prio_802_1_qau_params *hw_qcn;
621 hw_qcn =
631 hw_qcn->modify_enable_high = cpu_to_be32(
633 hw_qcn->modify_enable_low = cpu_to_be32(MODIFY_ENABLE_LOW_MASK);
635 hw_qcn->extended_enable = cpu_to_be32(qcn->rpg_enable[i] << RPG_ENABLE_BIT);
636 hw_qcn->rppp_max_rps = cpu_to_be32(qcn->rppp_max_rps[i]);
637 hw_qcn->rpg_time_reset = cpu_to_be32(qcn->rpg_time_reset[i]);
638 hw_qcn->rpg_byte_reset = cpu_to_be32(qcn->rpg_byte_reset[i]);
639 hw_qcn->rpg_threshold = cpu_to_be32(qcn->rpg_threshold[i]);
640 hw_qcn->rpg_max_rate = cpu_to_be32(qcn->rpg_max_rate[i]);
641 hw_qcn->rpg_ai_rate = cpu_to_be32(qcn->rpg_ai_rate[i]);
642 hw_qcn->rpg_hai_rate = cpu_to_be32(qcn->rpg_hai_rate[i]);
643 hw_qcn->rpg_gd = cpu_to_be32(qcn->rpg_gd[i]);
644 hw_qcn->rpg_min_dec_fac = cpu_to_be32(qcn->rpg_min_dec_fac[i]);
645 hw_qcn->rpg_min_rate = cpu_to_be32(qcn->rpg_min_rate[i]);
648 hw_qcn->extended_enable |= cpu_to_be32(1 << CN_TAG_BIT);