Lines Matching refs:hw
151 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
155 gma_write16(hw, port, GM_SMI_DATA, val);
156 gma_write16(hw, port, GM_SMI_CTRL,
160 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
174 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
178 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
182 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
186 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
191 *val = gma_read16(hw, port, GM_SMI_DATA);
198 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
205 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 __gm_phy_read(hw, port, reg, &v);
213 static void sky2_power_on(struct sky2_hw *hw)
216 sky2_write8(hw, B0_POWER_CTRL,
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
224 sky2_write8(hw, B2_Y2_CLK_GATE,
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
231 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
236 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
241 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
246 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
248 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
251 reg = sky2_read32(hw, B2_GP_IO);
253 sky2_write32(hw, B2_GP_IO, reg);
255 sky2_read32(hw, B2_GP_IO);
259 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
262 static void sky2_power_aux(struct sky2_hw *hw)
264 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
265 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 sky2_write8(hw, B2_Y2_CLK_GATE,
274 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
275 pci_pme_capable(hw->pdev, PCI_D3cold))
276 sky2_write8(hw, B0_POWER_CTRL,
281 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
284 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
291 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
292 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
293 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296 reg = gma_read16(hw, port, GM_RX_CTRL);
298 gma_write16(hw, port, GM_RX_CTRL, reg);
326 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
332 !(hw->flags & SKY2_HW_NEWER_PHY)) {
333 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
340 if (hw->chip_id == CHIP_ID_YUKON_EC)
347 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
351 if (sky2_is_copper(hw)) {
352 if (!(hw->flags & SKY2_HW_GIGABIT)) {
356 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
357 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
374 (hw->flags & SKY2_HW_NEWER_PHY)) {
387 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
391 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
394 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
395 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400 if (hw->pmd_type == 'P') {
402 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
410 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
419 if (sky2_is_copper(hw)) {
468 if (sky2_is_copper(hw))
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
483 gma_write16(hw, port, GM_GP_CTRL, reg);
485 if (hw->flags & SKY2_HW_GIGABIT)
486 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
488 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
489 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
495 switch (hw->chip_id) {
500 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
506 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
523 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
527 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
533 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
549 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
555 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
558 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
561 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
582 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
587 gm_phy_write(hw, port, 0x18, 0xaa99);
588 gm_phy_write(hw, port, 0x17, 0x2011);
590 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
592 gm_phy_write(hw, port, 0x18, 0xa204);
593 gm_phy_write(hw, port, 0x17, 0x2002);
597 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
598 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
599 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
601 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
602 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
603 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
605 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
608 gm_phy_write(hw, port, 24, 0x2800);
609 gm_phy_write(hw, port, 23, 0x2001);
612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
613 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
614 hw->chip_id < CHIP_ID_YUKON_SUPR) {
616 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
625 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
627 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
628 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
655 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
657 gm_phy_write(hw, port, 1, 0x4099);
658 gm_phy_write(hw, port, 3, 0x1120);
659 gm_phy_write(hw, port, 11, 0x113c);
660 gm_phy_write(hw, port, 14, 0x8100);
661 gm_phy_write(hw, port, 15, 0x112a);
662 gm_phy_write(hw, port, 17, 0x1008);
664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
665 gm_phy_write(hw, port, 1, 0x20b0);
667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
671 gm_phy_write(hw, port, 17, eee_afe[i].val);
672 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
676 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
679 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
680 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
681 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
688 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
690 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
696 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
700 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
701 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
704 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
707 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
708 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
709 sky2_pci_read32(hw, PCI_DEV_REG1);
711 if (hw->chip_id == CHIP_ID_YUKON_FE)
712 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
713 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
714 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
717 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
723 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
726 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
728 if (hw->flags & SKY2_HW_NEWER_PHY) {
730 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
732 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
735 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
738 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
742 gma_write16(hw, port, GM_GP_CTRL,
747 if (hw->chip_id != CHIP_ID_YUKON_EC) {
748 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
750 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
752 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
755 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
758 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
762 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
765 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
766 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
768 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
769 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
777 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
783 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
789 struct sky2_hw *hw = sky2->hw;
793 reg = gma_read16(hw, port, GM_GP_CTRL);
795 gma_write16(hw, port, GM_GP_CTRL, reg);
802 sky2_phy_init(sky2->hw, sky2->port);
810 struct sky2_hw *hw = sky2->hw;
816 sky2_write16(hw, B0_CTST, CS_RST_CLR);
817 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
820 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
840 gma_write16(hw, port, GM_GP_CTRL,
845 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
849 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
862 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
865 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
869 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
871 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
875 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
876 sky2_read32(hw, B0_CTST);
879 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
881 struct net_device *dev = hw->dev[port];
883 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
884 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
885 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
887 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
890 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
893 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
895 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
898 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
900 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
904 const u8 *addr = hw->dev[port]->dev_addr;
906 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
907 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
909 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
911 if (hw->chip_id == CHIP_ID_YUKON_XL &&
912 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
916 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
918 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
919 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
920 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
921 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
922 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
925 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
928 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
931 sky2_phy_power_up(hw, port);
932 sky2_phy_init(hw, port);
936 reg = gma_read16(hw, port, GM_PHY_ADDR);
937 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
940 gma_read16(hw, port, i);
941 gma_write16(hw, port, GM_PHY_ADDR, reg);
944 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
947 gma_write16(hw, port, GM_RX_CTRL,
951 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
954 gma_write16(hw, port, GM_TX_PARAM,
964 if (hw->dev[port]->mtu > ETH_DATA_LEN)
967 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
968 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
971 gma_write16(hw, port, GM_SERIAL_MODE, reg);
974 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
977 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
980 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
981 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
982 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
985 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
987 if (hw->chip_id == CHIP_ID_YUKON_EX ||
988 hw->chip_id == CHIP_ID_YUKON_FE_P)
991 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
993 if (hw->chip_id == CHIP_ID_YUKON_XL) {
995 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
998 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1004 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1005 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1007 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1010 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1011 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1014 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1016 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1017 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1021 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1022 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1024 sky2_set_tx_stfwd(hw, port);
1027 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1028 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1030 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1032 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1037 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1041 /* convert from K bytes to qwords used for hw register */
1046 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1047 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1048 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1049 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1050 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1059 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1060 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1063 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1064 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1069 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1072 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1073 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1077 static void sky2_qset(struct sky2_hw *hw, u16 q)
1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1081 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1082 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1088 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1093 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1094 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1095 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1096 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1098 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1126 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1130 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1275 sky2_write32(sky2->hw,
1285 struct sky2_hw *hw = sky2->hw;
1289 if (hw->flags & SKY2_HW_NEW_LE) {
1291 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1300 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1304 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1307 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1310 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1326 struct sky2_hw *hw = sky2->hw;
1331 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1334 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1335 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1340 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1343 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1358 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1370 struct sky2_hw *hw = sky2->hw;
1385 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1394 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1407 struct sky2_hw *hw = sky2->hw;
1411 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1414 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1418 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1423 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1426 /* Can't do transmit offload of vlan without hw vlan */
1432 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1434 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1447 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1452 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1482 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1487 struct sky2_hw *hw = sky2->hw;
1500 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1520 struct sky2_hw *hw = sky2->hw;
1526 sky2_qset(hw, rxq);
1529 if (pci_is_pcie(hw->pdev))
1530 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1535 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1536 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1537 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1539 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1541 if (!(hw->flags & SKY2_HW_NEW_LE))
1544 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1561 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1563 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1564 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1570 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1571 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1579 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1582 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1584 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1588 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1595 struct sky2_hw *hw = sky2->hw;
1598 sky2->tx_le = dma_alloc_coherent(&hw->pdev->dev,
1609 sky2->rx_le = dma_alloc_coherent(&hw->pdev->dev, RX_LE_BYTES,
1626 struct sky2_hw *hw = sky2->hw;
1631 dma_free_coherent(&hw->pdev->dev, RX_LE_BYTES, sky2->rx_le,
1636 dma_free_coherent(&hw->pdev->dev,
1650 struct sky2_hw *hw = sky2->hw;
1654 struct net_device *otherdev = hw->dev[sky2->port^1];
1663 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1666 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1668 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1671 sky2_mac_init(hw, port);
1674 ramsize = sky2_read8(hw, B2_E_0) * 4;
1684 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1685 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1688 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1692 sky2_qset(hw, txqaddr[port]);
1695 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1696 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1699 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1700 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1701 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1703 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1713 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1715 struct pci_dev *pdev = hw->pdev;
1719 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1720 name, hw);
1724 hw->flags |= SKY2_HW_IRQ_SETUP;
1726 napi_enable(&hw->napi);
1727 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1728 sky2_read32(hw, B0_IMSK);
1739 struct sky2_hw *hw = sky2->hw;
1751 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1757 imask = sky2_read32(hw, B0_IMSK);
1759 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1760 hw->chip_id == CHIP_ID_YUKON_PRM ||
1761 hw->chip_id == CHIP_ID_YUKON_OP_2)
1765 sky2_write32(hw, B0_IMSK, imask);
1766 sky2_read32(hw, B0_IMSK);
1829 struct sky2_hw *hw = sky2->hw;
1843 mapping = dma_map_single(&hw->pdev->dev, skb->data, len,
1846 if (dma_mapping_error(&hw->pdev->dev, mapping))
1866 if (!(hw->flags & SKY2_HW_NEW_LE))
1873 if (hw->flags & SKY2_HW_NEW_LE)
1898 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1938 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1941 if (dma_mapping_error(&hw->pdev->dev, mapping))
1973 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1981 sky2_tx_unmap(hw->pdev, re);
1986 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2014 sky2_tx_unmap(sky2->hw->pdev, re);
2041 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2044 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2048 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2049 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2052 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2056 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2059 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2060 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2062 sky2_read32(hw, B0_CTST);
2067 struct sky2_hw *hw = sky2->hw;
2072 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2075 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2076 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2078 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2081 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2083 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2085 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2088 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2089 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2090 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2092 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2095 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2096 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2097 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2098 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2103 sky2_phy_power_down(hw, port);
2106 sky2_tx_reset(hw, port);
2116 struct sky2_hw *hw = sky2->hw;
2124 if (hw->ports == 1) {
2125 sky2_write32(hw, B0_IMSK, 0);
2126 sky2_read32(hw, B0_IMSK);
2128 napi_disable(&hw->napi);
2129 free_irq(hw->pdev->irq, hw);
2130 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2135 imask = sky2_read32(hw, B0_IMSK);
2137 sky2_write32(hw, B0_IMSK, imask);
2138 sky2_read32(hw, B0_IMSK);
2140 synchronize_irq(hw->pdev->irq);
2141 napi_synchronize(&hw->napi);
2151 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2153 if (hw->flags & SKY2_HW_FIBRE_PHY)
2156 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2175 struct sky2_hw *hw = sky2->hw;
2188 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2192 mod_timer(&hw->watchdog_timer, jiffies + 1);
2195 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2207 struct sky2_hw *hw = sky2->hw;
2211 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2213 reg = gma_read16(hw, port, GM_GP_CTRL);
2215 gma_write16(hw, port, GM_GP_CTRL, reg);
2220 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2224 sky2_phy_init(hw, port);
2237 struct sky2_hw *hw = sky2->hw;
2241 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2242 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2253 sky2->speed = sky2_phy_speed(hw, aux);
2259 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2286 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2290 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2292 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2298 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2300 struct net_device *dev = hw->dev[port];
2308 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2309 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2322 sky2->speed = sky2_phy_speed(hw, phystat);
2339 static void sky2_qlink_intr(struct sky2_hw *hw)
2341 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2346 imask = sky2_read32(hw, B0_IMSK);
2348 sky2_write32(hw, B0_IMSK, imask);
2351 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2353 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2354 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2365 struct sky2_hw *hw = sky2->hw;
2371 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2372 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2375 schedule_work(&hw->restart_work);
2381 struct sky2_hw *hw = sky2->hw;
2393 imask = sky2_read32(hw, B0_IMSK);
2394 sky2_write32(hw, B0_IMSK, 0);
2395 sky2_read32(hw, B0_IMSK);
2398 napi_disable(&hw->napi);
2401 synchronize_irq(hw->pdev->irq);
2403 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2404 sky2_set_tx_stfwd(hw, port);
2406 ctl = gma_read16(hw, port, GM_GP_CTRL);
2407 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2423 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2425 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2432 sky2_write32(hw, B0_IMSK, imask);
2434 sky2_read32(hw, B0_Y2_SP_LISR);
2435 napi_enable(&hw->napi);
2440 gma_write16(hw, port, GM_GP_CTRL, ctl);
2468 dma_sync_single_for_cpu(&sky2->hw->pdev->dev, re->data_addr,
2476 dma_sync_single_for_device(&sky2->hw->pdev->dev,
2533 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2537 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2579 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2580 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2637 napi_gro_receive(&sky2->hw->napi, skb);
2640 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2643 struct net_device *dev = hw->dev[port];
2661 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2673 dev_notice(&sky2->hw->pdev->dev,
2682 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2704 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2716 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2727 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2730 dev = hw->dev[port];
2746 if (hw->flags & SKY2_HW_NEW_LE) {
2781 sky2_tx_done(hw->dev[0], status & 0xfff);
2782 if (hw->dev[1])
2783 sky2_tx_done(hw->dev[1],
2792 } while (hw->st_idx != idx);
2795 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2798 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2799 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2804 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2806 struct net_device *dev = hw->dev[port];
2809 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2815 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2822 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2828 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2834 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2840 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2844 static void sky2_hw_intr(struct sky2_hw *hw)
2846 struct pci_dev *pdev = hw->pdev;
2847 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2848 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2853 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2858 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2859 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2864 sky2_pci_write16(hw, PCI_STATUS,
2866 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2873 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2874 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2875 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2880 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2881 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2885 sky2_hw_error(hw, 0, status);
2888 sky2_hw_error(hw, 1, status);
2891 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2893 struct net_device *dev = hw->dev[port];
2895 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2900 gma_read16(hw, port, GM_RX_IRQ_SRC);
2903 gma_read16(hw, port, GM_TX_IRQ_SRC);
2907 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2912 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2917 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2919 struct net_device *dev = hw->dev[port];
2920 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2922 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2924 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2926 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2932 struct sky2_hw *hw = sky2->hw;
2935 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2936 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2937 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2938 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2950 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2964 struct sky2_hw *hw = timer_container_of(hw, t, watchdog_timer);
2967 if (sky2_read32(hw, B0_ISRC)) {
2968 napi_schedule(&hw->napi);
2972 for (i = 0; i < hw->ports; i++) {
2973 struct net_device *dev = hw->dev[i];
2979 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2982 schedule_work(&hw->restart_work);
2991 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2995 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2998 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
3001 sky2_hw_intr(hw);
3004 sky2_mac_intr(hw, 0);
3007 sky2_mac_intr(hw, 1);
3010 sky2_le_error(hw, 0, Q_R1);
3013 sky2_le_error(hw, 1, Q_R2);
3016 sky2_le_error(hw, 0, Q_XA1);
3019 sky2_le_error(hw, 1, Q_XA2);
3024 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3025 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3030 sky2_err_intr(hw, status);
3033 sky2_phy_intr(hw, 0);
3036 sky2_phy_intr(hw, 1);
3039 sky2_qlink_intr(hw);
3041 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3042 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3049 sky2_read32(hw, B0_Y2_SP_LISR);
3057 struct sky2_hw *hw = dev_id;
3061 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3063 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3067 prefetch(&hw->st_le[hw->st_idx]);
3069 napi_schedule(&hw->napi);
3079 napi_schedule(&sky2->hw->napi);
3084 static u32 sky2_mhz(const struct sky2_hw *hw)
3086 switch (hw->chip_id) {
3111 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3113 return sky2_mhz(hw) * us;
3116 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3118 return clk / sky2_mhz(hw);
3122 static int sky2_init(struct sky2_hw *hw)
3127 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3129 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3131 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3132 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3134 switch (hw->chip_id) {
3136 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3137 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3138 hw->flags |= SKY2_HW_RSS_BROKEN;
3142 hw->flags = SKY2_HW_GIGABIT
3148 hw->flags = SKY2_HW_GIGABIT
3155 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3156 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3161 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3162 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3165 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3169 hw->flags = SKY2_HW_RSS_BROKEN;
3173 hw->flags = SKY2_HW_NEWER_PHY
3179 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3180 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3184 hw->flags = SKY2_HW_GIGABIT
3190 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3191 hw->flags |= SKY2_HW_RSS_CHKSUM;
3195 hw->flags = SKY2_HW_GIGABIT
3202 hw->flags = SKY2_HW_GIGABIT
3208 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3209 hw->chip_id);
3213 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3214 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3215 hw->flags |= SKY2_HW_FIBRE_PHY;
3217 hw->ports = 1;
3218 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3220 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3221 ++hw->ports;
3224 if (sky2_read8(hw, B2_E_0))
3225 hw->flags |= SKY2_HW_RAM_BUFFER;
3230 static void sky2_reset(struct sky2_hw *hw)
3232 struct pci_dev *pdev = hw->pdev;
3238 if (hw->chip_id == CHIP_ID_YUKON_EX
3239 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3240 sky2_write32(hw, CPU_WDOG, 0);
3241 status = sky2_read16(hw, HCU_CCSR);
3250 sky2_write16(hw, HCU_CCSR, status);
3251 sky2_write32(hw, CPU_WDOG, 0);
3253 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3254 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3257 sky2_write8(hw, B0_CTST, CS_RST_SET);
3258 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3261 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3264 status = sky2_pci_read16(hw, PCI_STATUS);
3266 sky2_pci_write16(hw, PCI_STATUS, status);
3268 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3271 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3275 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3281 sky2_power_on(hw);
3282 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3284 for (i = 0; i < hw->ports; i++) {
3285 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3286 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3288 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3289 hw->chip_id == CHIP_ID_YUKON_SUPR)
3290 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3296 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3298 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3301 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3302 hw->chip_id == CHIP_ID_YUKON_PRM ||
3303 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3306 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3308 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3314 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3324 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3325 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3328 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3331 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3334 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3335 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3337 reg = sky2_read16(hw, GPHY_CTRL);
3338 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3341 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3342 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3345 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3348 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3352 sky2_write32(hw, B2_I2C_IRQ, 1);
3355 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3356 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3359 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3362 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3363 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3366 for (i = 0; i < hw->ports; i++)
3367 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3370 for (i = 0; i < hw->ports; i++) {
3371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3373 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3374 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3375 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3376 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3377 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3387 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3389 for (i = 0; i < hw->ports; i++)
3390 sky2_gmac_reset(hw, i);
3392 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3393 hw->st_idx = 0;
3395 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3396 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3398 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3399 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3402 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3404 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3405 sky2_write8(hw, STAT_FIFO_WM, 16);
3408 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3409 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3411 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3413 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3414 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3415 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3418 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3420 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3421 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3422 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3458 static void sky2_all_down(struct sky2_hw *hw)
3462 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3463 sky2_write32(hw, B0_IMSK, 0);
3464 sky2_read32(hw, B0_IMSK);
3466 synchronize_irq(hw->pdev->irq);
3467 napi_disable(&hw->napi);
3470 for (i = 0; i < hw->ports; i++) {
3471 struct net_device *dev = hw->dev[i];
3483 static void sky2_all_up(struct sky2_hw *hw)
3488 for (i = 0; i < hw->ports; i++) {
3489 struct net_device *dev = hw->dev[i];
3501 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3502 sky2_write32(hw, B0_IMSK, imask);
3503 sky2_read32(hw, B0_IMSK);
3504 sky2_read32(hw, B0_Y2_SP_LISR);
3505 napi_enable(&hw->napi);
3511 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3515 sky2_all_down(hw);
3516 sky2_reset(hw);
3517 sky2_all_up(hw);
3522 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3524 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3531 wol->supported = sky2_wol_supported(sky2->hw);
3538 struct sky2_hw *hw = sky2->hw;
3542 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3543 !device_can_wakeup(&hw->pdev->dev))
3548 for (i = 0; i < hw->ports; i++) {
3549 struct net_device *dev = hw->dev[i];
3555 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3560 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3562 if (sky2_is_copper(hw)) {
3568 if (hw->flags & SKY2_HW_GIGABIT)
3581 struct sky2_hw *hw = sky2->hw;
3584 supported = sky2_supported_modes(hw);
3586 if (sky2_is_copper(hw)) {
3613 const struct sky2_hw *hw = sky2->hw;
3614 u32 supported = sky2_supported_modes(hw);
3624 if (sky2_is_copper(hw))
3693 strscpy(info->bus_info, pci_name(sky2->hw->pdev),
3762 struct sky2_hw *hw = sky2->hw;
3766 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3767 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3770 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3812 struct sky2_hw *hw = sky2->hw;
3820 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3822 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3826 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3829 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3845 struct sky2_hw *hw = sky2->hw;
3856 reg = gma_read16(hw, port, GM_RX_CTRL);
3875 gma_write16(hw, port, GM_MC_ADDR_H1,
3877 gma_write16(hw, port, GM_MC_ADDR_H2,
3879 gma_write16(hw, port, GM_MC_ADDR_H3,
3881 gma_write16(hw, port, GM_MC_ADDR_H4,
3884 gma_write16(hw, port, GM_RX_CTRL, reg);
3891 struct sky2_hw *hw = sky2->hw;
3914 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3915 + get_stats32(hw, port, GM_RXF_BC_OK);
3917 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3919 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3920 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3921 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3922 + get_stats32(hw, port, GM_RXE_FRAG);
3923 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3935 struct sky2_hw *hw = sky2->hw;
3939 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3940 hw->chip_id == CHIP_ID_YUKON_EX ||
3941 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3943 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3944 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3948 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3955 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3962 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3969 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3976 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3978 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
4059 struct sky2_hw *hw = sky2->hw;
4061 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4064 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4065 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4067 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4069 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4072 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4073 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4075 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4077 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4080 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4081 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4084 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4096 struct sky2_hw *hw = sky2->hw;
4097 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4112 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4114 sky2_write32(hw, STAT_TX_TIMER_INI,
4115 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4116 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4118 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4121 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4123 sky2_write32(hw, STAT_LEV_TIMER_INI,
4124 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4125 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4127 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4130 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4132 sky2_write32(hw, STAT_ISR_TIMER_INI,
4133 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4134 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4136 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4191 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4210 return hw->ports > 1;
4243 const void __iomem *io = sky2->hw->regs;
4252 else if (sky2_reg_access_ok(sky2->hw, b))
4265 struct sky2_hw *hw = sky2->hw;
4268 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4279 rc = pci_read_vpd_any(sky2->hw->pdev, eeprom->offset, eeprom->len,
4298 rc = pci_write_vpd_any(sky2->hw->pdev, eeprom->offset, eeprom->len,
4308 const struct sky2_hw *hw = sky2->hw;
4313 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4321 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4335 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4336 sky2_write32(sky2->hw,
4390 struct sky2_hw *hw = sky2->hw;
4396 sky2_read32(hw, B0_ISRC),
4397 sky2_read32(hw, B0_IMSK),
4398 sky2_read32(hw, B0_Y2_SP_ICR));
4405 napi_disable(&hw->napi);
4406 last = sky2_read16(hw, STAT_PUT_IDX);
4408 seq_printf(seq, "Status ring %u\n", hw->st_size);
4409 if (hw->st_idx == last)
4413 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4414 idx = RING_NEXT(idx, hw->st_size)) {
4415 const struct sky2_status_le *le = hw->st_le + idx;
4424 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4425 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4471 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4472 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4473 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4474 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4476 sky2_read32(hw, B0_Y2_SP_LISR);
4477 napi_enable(&hw->napi);
4588 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4598 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4599 dev->irq = hw->pdev->irq;
4606 sky2->hw = hw;
4614 if (hw->chip_id != CHIP_ID_YUKON_XL)
4621 sky2->advertising = sky2_supported_modes(hw);
4630 hw->dev[port] = dev;
4640 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4643 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4653 if (hw->chip_id == CHIP_ID_YUKON_FE ||
4654 hw->chip_id == CHIP_ID_YUKON_FE_P)
4663 ret = of_get_ethdev_address(hw->pdev->dev.of_node, dev);
4667 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4675 dev_warn(&hw->pdev->dev, "Invalid MAC address, defaulting to random\n");
4679 dev_warn(&hw->pdev->dev, "Failed to set MAC address.\n");
4695 struct sky2_hw *hw = dev_id;
4696 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4702 hw->flags |= SKY2_HW_USE_MSI;
4703 wake_up(&hw->msi_wait);
4704 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4706 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4712 static int sky2_test_msi(struct sky2_hw *hw)
4714 struct pci_dev *pdev = hw->pdev;
4717 init_waitqueue_head(&hw->msi_wait);
4719 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4725 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4727 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4728 sky2_read8(hw, B0_CTST);
4730 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4732 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4738 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4741 sky2_write32(hw, B0_IMSK, 0);
4742 sky2_read32(hw, B0_IMSK);
4744 free_irq(pdev->irq, hw);
4816 struct sky2_hw *hw;
4886 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4888 if (!hw)
4891 hw->pdev = pdev;
4892 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4894 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
4895 if (!hw->regs) {
4900 err = sky2_init(hw);
4905 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4906 hw->st_le = dma_alloc_coherent(&pdev->dev,
4907 hw->st_size * sizeof(struct sky2_status_le),
4908 &hw->st_dma, GFP_KERNEL);
4909 if (!hw->st_le) {
4915 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4917 sky2_reset(hw);
4919 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4929 err = sky2_test_msi(hw);
4937 netif_napi_add(dev, &hw->napi, sky2_poll);
4949 if (hw->ports > 1) {
4950 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4962 err = sky2_setup_irq(hw, hw->irq_name);
4969 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0);
4970 INIT_WORK(&hw->restart_work, sky2_restart);
4972 pci_set_drvdata(pdev, hw);
4984 if (hw->flags & SKY2_HW_USE_MSI)
4989 hw->st_size * sizeof(struct sky2_status_le),
4990 hw->st_le, hw->st_dma);
4992 sky2_write8(hw, B0_CTST, CS_RST_SET);
4994 iounmap(hw->regs);
4996 kfree(hw);
5007 struct sky2_hw *hw = pci_get_drvdata(pdev);
5010 if (!hw)
5013 timer_shutdown_sync(&hw->watchdog_timer);
5014 cancel_work_sync(&hw->restart_work);
5016 for (i = hw->ports-1; i >= 0; --i)
5017 unregister_netdev(hw->dev[i]);
5019 sky2_write32(hw, B0_IMSK, 0);
5020 sky2_read32(hw, B0_IMSK);
5022 sky2_power_aux(hw);
5024 sky2_write8(hw, B0_CTST, CS_RST_SET);
5025 sky2_read8(hw, B0_CTST);
5027 if (hw->ports > 1) {
5028 napi_disable(&hw->napi);
5029 free_irq(pdev->irq, hw);
5032 if (hw->flags & SKY2_HW_USE_MSI)
5035 hw->st_size * sizeof(struct sky2_status_le),
5036 hw->st_le, hw->st_dma);
5040 for (i = hw->ports-1; i >= 0; --i)
5041 free_netdev(hw->dev[i]);
5043 iounmap(hw->regs);
5044 kfree(hw);
5049 struct sky2_hw *hw = dev_get_drvdata(dev);
5052 if (!hw)
5055 timer_delete_sync(&hw->watchdog_timer);
5056 cancel_work_sync(&hw->restart_work);
5060 sky2_all_down(hw);
5061 for (i = 0; i < hw->ports; i++) {
5062 struct net_device *dev = hw->dev[i];
5069 sky2_power_aux(hw);
5079 struct sky2_hw *hw = pci_get_drvdata(pdev);
5082 if (!hw)
5093 sky2_reset(hw);
5094 sky2_all_up(hw);
5115 struct sky2_hw *hw = pci_get_drvdata(pdev);
5118 for (port = 0; port < hw->ports; port++) {
5119 struct net_device *ndev = hw->dev[port];