15 #define RVU_PRIV_PFX_DISC(a)			(0x8000208 | (a) << 16)  argument
16 #define RVU_PRIV_HWVFX_DISC(a)			(0xD000000 | (a) << 12)  argument
20 #define RVU_MBOX_AF_PFX_ADDR(a)			(0x5000 | (a) << 4)  argument
21 #define RVU_MBOX_AF_PFX_CFG(a)			(0x6000 | (a) << 4)  argument
22 #define RVU_MBOX_AF_AFPFX_TRIGX(a)		(0x9000 | (a) << 3)  argument
23 #define RVU_MBOX_AF_PFAF_INT(a)			(0x2980 | (a) << 6)  argument
24 #define RVU_MBOX_AF_PFAF_INT_W1S(a)		(0x2988 | (a) << 6)  argument
25 #define RVU_MBOX_AF_PFAF_INT_ENA_W1S(a)		(0x2990 | (a) << 6)  argument
26 #define RVU_MBOX_AF_PFAF_INT_ENA_W1C(a)		(0x2998 | (a) << 6)  argument
27 #define RVU_MBOX_AF_PFAF1_INT(a)		(0x29A0 | (a) << 6)  argument
28 #define RVU_MBOX_AF_PFAF1_INT_W1S(a)		(0x29A8 | (a) << 6)  argument
29 #define RVU_MBOX_AF_PFAF1_INT_ENA_W1S(a)	(0x29B0 | (a) << 6)  argument
30 #define RVU_MBOX_AF_PFAF1_INT_ENA_W1C(a)	(0x29B8 | (a) << 6)  argument
33 #define RVU_MBOX_PF_PFAF_TRIGX(a)		(0xC00 | (a) << 3)  argument
41 #define NIX_CINTX_INT_W1S(a)			(0xd30 | (a) << 12)  argument
42 #define NIX_QINTX_CNT(a)			(0xc00 | (a) << 12)  argument
44 #define RVU_MBOX_AF_VFAF_INT(a)			(0x3000 | (a) << 6)  argument
45 #define RVU_MBOX_AF_VFAF_INT_W1S(a)		(0x3008 | (a) << 6)  argument
46 #define RVU_MBOX_AF_VFAF_INT_ENA_W1S(a)		(0x3010 | (a) << 6)  argument
47 #define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a)		(0x3018 | (a) << 6)  argument
48 #define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a)		(0x3018 | (a) << 6)  argument
49 #define RVU_MBOX_AF_VFAF1_INT(a)		(0x3020 | (a) << 6)  argument
50 #define RVU_MBOX_AF_VFAF1_INT_W1S(a)		(0x3028 | (a) << 6)  argument
51 #define RVU_MBOX_AF_VFAF1_IN_ENA_W1S(a)		(0x3030 | (a) << 6)  argument
52 #define RVU_MBOX_AF_VFAF1_IN_ENA_W1C(a)		(0x3038 | (a) << 6)  argument
54 #define RVU_MBOX_AF_AFVFX_TRIG(a, b)		(0x10000 | (a) << 4 | (b) << 3)  argument
55 #define RVU_MBOX_AF_VFX_ADDR(a)			(0x20000 | (a) << 4)  argument
56 #define RVU_MBOX_AF_VFX_CFG(a)			(0x28000 | (a) << 4)  argument
58 #define RVU_MBOX_PF_VFX_PFVF_TRIGX(a)		(0x2000 | (a) << 3)  argument
60 #define RVU_MBOX_PF_VFPF_INTX(a)		(0x1000 | (a) << 3)  argument
61 #define RVU_MBOX_PF_VFPF_INT_W1SX(a)		(0x1020 | (a) << 3)  argument
62 #define RVU_MBOX_PF_VFPF_INT_ENA_W1SX(a)	(0x1040 | (a) << 3)  argument
63 #define RVU_MBOX_PF_VFPF_INT_ENA_W1CX(a)	(0x1060 | (a) << 3)  argument
65 #define RVU_MBOX_PF_VFPF1_INTX(a)		(0x1080 | (a) << 3)  argument
66 #define RVU_MBOX_PF_VFPF1_INT_W1SX(a)		(0x10a0 | (a) << 3)  argument
67 #define RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(a)	(0x10c0 | (a) << 3)  argument
68 #define RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(a)	(0x10e0 | (a) << 3)  argument
74 #define RVU_MBOX_VF_VFPF_TRIGX(a)		(0x3000 | (a) << 3)  argument
80 #define RVU_MBOX_VF_VFAF_TRIGX(a)		(0x2000 | (a) << 3)  argument