Lines Matching refs:hw
20 static int ixgbe_update_flash_X540(struct ixgbe_hw *hw);
21 static int ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
22 static int ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
23 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
25 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
30 int ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
32 struct ixgbe_mac_info *mac = &hw->mac;
33 struct ixgbe_phy_info *phy = &hw->phy;
44 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
51 * @hw: pointer to hardware structure
55 int ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
58 return hw->phy.ops.setup_link_speed(hw, speed,
64 * @hw: pointer to hardware structure
72 int ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
74 u32 swfw_mask = hw->phy.phy_semaphore_mask;
79 status = hw->mac.ops.stop_adapter(hw);
84 ixgbe_clear_tx_pending(hw);
87 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
89 hw_dbg(hw, "semaphore failed with %d", status);
94 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
95 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
96 IXGBE_WRITE_FLUSH(hw);
97 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
102 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
110 hw_dbg(hw, "Reset polling failed to complete.\n");
119 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
120 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
125 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
128 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
135 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
136 hw->mac.ops.init_rx_addrs(hw);
139 if (hw->mac.type == ixgbe_mac_e610)
143 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
146 if (is_valid_ether_addr(hw->mac.san_addr)) {
148 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
150 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
151 hw->mac.san_addr, 0, IXGBE_RAH_AV);
154 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
158 hw->mac.num_rar_entries--;
162 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
163 &hw->mac.wwpn_prefix);
170 * @hw: pointer to hardware structure
176 int ixgbe_start_hw_X540(struct ixgbe_hw *hw)
180 ret_val = ixgbe_start_hw_generic(hw);
184 return ixgbe_start_hw_gen2(hw);
189 * @hw: pointer to hardware structure
194 int ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
196 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
205 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
210 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
219 * @hw: pointer to hardware structure
225 static int ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
229 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
232 status = ixgbe_read_eerd_generic(hw, offset, data);
234 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
240 * @hw: pointer to hardware structure
247 static int ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
252 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
255 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
257 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
263 * @hw: pointer to hardware structure
269 static int ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
273 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
276 status = ixgbe_write_eewr_generic(hw, offset, data);
278 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
284 * @hw: pointer to hardware structure
291 static int ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
296 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
299 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
301 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
311 * @hw: pointer to hardware structure
313 static int ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
325 * Do not use hw->eeprom.ops.read because we do not want to take
332 if (ixgbe_read_eerd_generic(hw, i, &word)) {
333 hw_dbg(hw, "EEPROM read failed\n");
347 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
348 hw_dbg(hw, "EEPROM read failed\n");
354 pointer >= hw->eeprom.word_size)
357 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
358 hw_dbg(hw, "EEPROM read failed\n");
364 (pointer + length) >= hw->eeprom.word_size)
368 if (ixgbe_read_eerd_generic(hw, j, &word)) {
369 hw_dbg(hw, "EEPROM read failed\n");
383 * @hw: pointer to hardware structure
389 static int ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
400 status = hw->eeprom.ops.read(hw, 0, &checksum);
402 hw_dbg(hw, "EEPROM read failed\n");
406 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
409 status = hw->eeprom.ops.calc_checksum(hw);
415 /* Do not use hw->eeprom.ops.read because we do not want to take
418 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
427 hw_dbg(hw, "Invalid EEPROM checksum");
436 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
443 * @hw: pointer to hardware structure
449 static int ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
458 status = hw->eeprom.ops.read(hw, 0, &checksum);
460 hw_dbg(hw, "EEPROM read failed\n");
464 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
467 status = hw->eeprom.ops.calc_checksum(hw);
473 /* Do not use hw->eeprom.ops.write because we do not want to
476 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
480 status = ixgbe_update_flash_X540(hw);
483 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
489 * @hw: pointer to hardware structure
494 static int ixgbe_update_flash_X540(struct ixgbe_hw *hw)
499 status = ixgbe_poll_flash_update_done_X540(hw);
501 hw_dbg(hw, "Flash update time out\n");
505 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
506 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
508 status = ixgbe_poll_flash_update_done_X540(hw);
510 hw_dbg(hw, "Flash update complete\n");
512 hw_dbg(hw, "Flash update time out\n");
514 if (hw->revision_id == 0) {
515 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
519 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
522 status = ixgbe_poll_flash_update_done_X540(hw);
524 hw_dbg(hw, "Flash update complete\n");
526 hw_dbg(hw, "Flash update time out\n");
534 * @hw: pointer to hardware structure
539 static int ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
545 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
555 * @hw: pointer to hardware structure
561 int ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
584 if (ixgbe_get_swfw_sync_semaphore(hw))
587 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
590 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
591 ixgbe_release_swfw_sync_semaphore(hw);
599 ixgbe_release_swfw_sync_semaphore(hw);
608 if (ixgbe_get_swfw_sync_semaphore(hw))
610 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
613 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
614 ixgbe_release_swfw_sync_semaphore(hw);
630 ixgbe_release_swfw_sync_X540(hw, rmask);
631 ixgbe_release_swfw_sync_semaphore(hw);
634 ixgbe_release_swfw_sync_semaphore(hw);
641 * @hw: pointer to hardware structure
647 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
654 ixgbe_get_swfw_sync_semaphore(hw);
656 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
658 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
660 ixgbe_release_swfw_sync_semaphore(hw);
666 * @hw: pointer to hardware structure
670 static int ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
681 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
688 hw_dbg(hw,
695 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
705 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
706 ixgbe_release_swfw_sync_semaphore(hw);
712 * @hw: pointer to hardware structure
716 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
722 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
724 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
726 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
728 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
730 IXGBE_WRITE_FLUSH(hw);
735 * @hw: pointer to hardware structure
740 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
750 ixgbe_get_swfw_sync_semaphore(hw);
751 ixgbe_release_swfw_sync_semaphore(hw);
758 ixgbe_acquire_swfw_sync_X540(hw, rmask);
759 ixgbe_release_swfw_sync_X540(hw, rmask);
764 * @hw: pointer to hardware structure
770 int ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
784 hw->mac.ops.check_link(hw, &speed, &link_up, false);
786 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
788 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
791 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
794 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
795 IXGBE_WRITE_FLUSH(hw);
802 * @hw: pointer to hardware structure
808 int ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
817 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
821 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
824 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
826 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
827 IXGBE_WRITE_FLUSH(hw);