intel/fm10k/fm10k_mbx.c

650 	crc = fm10k_crc_16b(&mbx->mbx_hdr, mbx->remote, 1);
790 	if (mbx->mbx_hdr)
802 	mbx->mbx_hdr = fm10k_read_reg(hw, mbx->mbmem_reg ^ mbx->mbmem_len);
819 	fm10k_write_reg(hw, mbmem, mbx->mbx_hdr);
826 	mbx->mbx_hdr = 0;
840 	mbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(FM10K_MSG_CONNECT, TYPE) |
868 	mbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC);
887 	mbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC);
908 	mbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC);
937 	mbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(FM10K_MSG_ERROR, TYPE) |
953 	const u32 *hdr = &mbx->mbx_hdr;
1066 	head = FM10K_MSG_HDR_FIELD_GET(mbx->mbx_hdr, HEAD);
1151 	const u32 *hdr = &mbx->mbx_hdr;
1197 	const u32 *hdr = &mbx->mbx_hdr;
1240 	const u32 *hdr = &mbx->mbx_hdr;
1292 	const u32 *hdr = &mbx->mbx_hdr;
1355 	switch (FM10K_MSG_HDR_FIELD_GET(mbx->mbx_hdr, TYPE)) {
1456 	fm10k_write_reg(hw, mbx->mbmem_reg ^ mbx->mbmem_len, mbx->mbx_hdr);
1636 	mbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(mbx->tail, SM_TAIL) |
1653 	mbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(mbx->tail, SM_TAIL) |
1774 	const u32 *hdr = &mbx->mbx_hdr;
2042 	const u32 *hdr = &mbx->mbx_hdr;
2102 	if (FM10K_MSG_HDR_FIELD_GET(mbx->mbx_hdr, SM_ERR)) {
2107 	switch (FM10K_MSG_HDR_FIELD_GET(mbx->mbx_hdr, SM_VER)) {