Lines Matching refs:ret_val
180 s32 ret_val = 0;
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
219 if (ret_val)
300 s32 ret_val;
315 ret_val = e1e_rphy_locked(hw, I217_PHY_TIMEOUTS_REG,
317 if (ret_val)
318 return ret_val;
338 s32 ret_val;
349 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
350 if (ret_val)
353 ret_val = hw->phy.ops.acquire(hw);
354 if (ret_val) {
414 ret_val = -E1000_ERR_PHY;
434 ret_val = -E1000_ERR_PHY;
444 if (!ret_val) {
457 ret_val = e1000e_phy_hw_reset_generic(hw);
458 if (ret_val)
467 ret_val = hw->phy.ops.check_reset_block(hw);
468 if (ret_val) {
474 ret_val = hw->phy.ops.acquire(hw);
475 if (ret_val) {
479 ret_val = e1000_reconfigure_k1_exit_timeout(hw);
492 return ret_val;
504 s32 ret_val;
529 ret_val = e1000_init_phy_workarounds_pchlan(hw);
530 if (ret_val)
531 return ret_val;
536 ret_val = e1000e_get_phy_id(hw);
537 if (ret_val)
538 return ret_val;
555 ret_val = e1000_set_mdio_slow_mode_hv(hw);
556 if (ret_val)
557 return ret_val;
558 ret_val = e1000e_get_phy_id(hw);
559 if (ret_val)
560 return ret_val;
583 ret_val = -E1000_ERR_PHY;
587 return ret_val;
599 s32 ret_val;
611 ret_val = e1000e_determine_phy_address(hw);
612 if (ret_val) {
615 ret_val = e1000e_determine_phy_address(hw);
616 if (ret_val) {
618 return ret_val;
626 ret_val = e1000e_get_phy_id(hw);
627 if (ret_val)
628 return ret_val;
844 s32 ret_val;
846 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
847 if (ret_val)
848 return ret_val;
851 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
853 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
855 return ret_val;
901 s32 ret_val;
919 ret_val = hw->phy.ops.acquire(hw);
920 if (ret_val)
921 return ret_val;
923 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
924 if (ret_val)
933 ret_val = e1000_read_emi_reg_locked(hw, lpa,
935 if (ret_val)
939 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
940 if (ret_val)
964 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
966 if (ret_val)
970 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
975 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
976 if (ret_val)
979 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
983 return ret_val;
1001 s32 ret_val = 0;
1005 ret_val = hw->phy.ops.acquire(hw);
1006 if (ret_val)
1007 return ret_val;
1009 ret_val =
1012 if (ret_val)
1015 ret_val =
1020 if (ret_val)
1027 ret_val =
1042 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
1043 if (ret_val)
1044 return ret_val;
1064 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
1065 if (ret_val)
1066 return ret_val;
1072 return ret_val;
1182 s32 ret_val;
1190 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl);
1191 if (ret_val) {
1193 return ret_val;
1222 s32 ret_val = 0;
1262 ret_val = hw->phy.ops.acquire(hw);
1263 if (ret_val)
1266 ret_val = e1000e_force_smbus(hw);
1267 if (ret_val) {
1268 e_dbg("Failed to force SMBUS: %d\n", ret_val);
1276 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1278 if (ret_val)
1284 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1287 if (ret_val)
1294 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1295 if (ret_val)
1325 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1327 if (ret_val)
1334 if (ret_val)
1335 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1339 return ret_val;
1359 s32 ret_val = 0;
1390 ret_val = -E1000_ERR_PHY;
1419 ret_val = hw->phy.ops.acquire(hw);
1420 if (ret_val)
1433 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1434 if (ret_val) {
1444 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1446 if (ret_val)
1462 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1463 if (ret_val)
1469 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1470 if (ret_val)
1498 if (ret_val)
1499 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1503 return ret_val;
1517 s32 ret_val, tipg_reg = 0;
1535 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1536 if (ret_val)
1540 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1541 if (ret_val)
1573 ret_val = hw->phy.ops.acquire(hw);
1574 if (ret_val)
1581 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1606 if (ret_val)
1614 ret_val = hw->phy.ops.acquire(hw);
1615 if (ret_val)
1618 ret_val = e1e_rphy_locked(hw,
1621 if (ret_val) {
1630 ret_val =
1636 if (ret_val)
1639 ret_val = hw->phy.ops.acquire(hw);
1640 if (ret_val)
1643 ret_val = e1e_wphy_locked(hw,
1647 if (ret_val)
1673 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1674 if (ret_val)
1681 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1682 if (ret_val)
1710 ret_val = e1000_k1_workaround_lv(hw);
1711 if (ret_val)
1712 return ret_val;
1716 ret_val = e1000_link_stall_workaround_hv(hw);
1717 if (ret_val)
1718 return ret_val;
1745 ret_val = e1000_set_eee_pchlan(hw);
1746 if (ret_val)
1747 return ret_val;
1767 ret_val = e1000e_config_fc_after_link_up(hw);
1768 if (ret_val)
1771 return ret_val;
1775 return ret_val;
1876 s32 ret_val = 0;
1895 ret_val = -E1000_ERR_CONFIG;
1918 ret_val = -E1000_ERR_CONFIG;
1923 if (ret_val)
1926 return ret_val;
2027 s32 ret_val;
2029 ret_val = e1000_acquire_swflag_ich8lan(hw);
2030 if (ret_val)
2138 s32 ret_val;
2140 ret_val = e1000_acquire_swflag_ich8lan(hw);
2142 if (ret_val)
2195 s32 ret_val;
2199 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2200 if (ret_val)
2201 return ret_val;
2234 s32 ret_val = 0;
2246 return ret_val;
2268 return ret_val;
2271 ret_val = hw->phy.ops.acquire(hw);
2272 if (ret_val)
2273 return ret_val;
2304 ret_val = e1000_write_smbus_addr(hw);
2305 if (ret_val)
2309 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2311 if (ret_val)
2321 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2322 if (ret_val)
2325 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2327 if (ret_val)
2339 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2340 if (ret_val)
2346 return ret_val;
2361 s32 ret_val = 0;
2369 ret_val = hw->phy.ops.acquire(hw);
2370 if (ret_val)
2371 return ret_val;
2376 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2378 if (ret_val)
2392 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2393 if (ret_val)
2407 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2408 if (ret_val)
2413 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2414 if (ret_val)
2418 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2423 return ret_val;
2438 s32 ret_val;
2444 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2446 if (ret_val)
2447 return ret_val;
2454 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2456 if (ret_val)
2457 return ret_val;
2489 s32 ret_val = 0;
2494 return ret_val;
2496 ret_val = hw->phy.ops.acquire(hw);
2497 if (ret_val)
2498 return ret_val;
2512 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2513 if (ret_val)
2539 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2544 return ret_val;
2553 s32 ret_val;
2556 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2557 if (ret_val)
2558 return ret_val;
2562 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2564 return ret_val;
2575 s32 ret_val = 0;
2583 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2584 if (ret_val)
2585 return ret_val;
2592 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2593 if (ret_val)
2594 return ret_val;
2597 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2598 if (ret_val)
2599 return ret_val;
2608 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2609 if (ret_val)
2610 return ret_val;
2615 ret_val = hw->phy.ops.acquire(hw);
2616 if (ret_val)
2617 return ret_val;
2620 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2622 if (ret_val)
2623 return ret_val;
2628 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2629 if (ret_val)
2630 return ret_val;
2633 ret_val = hw->phy.ops.acquire(hw);
2634 if (ret_val)
2635 return ret_val;
2636 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2637 if (ret_val)
2639 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2640 if (ret_val)
2644 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2648 return ret_val;
2659 s32 ret_val;
2661 ret_val = hw->phy.ops.acquire(hw);
2662 if (ret_val)
2664 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2665 if (ret_val)
2697 s32 ret_val = 0;
2707 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2708 if (ret_val)
2709 return ret_val;
2746 ret_val = e1000e_read_kmrn_reg(hw,
2749 if (ret_val)
2750 return ret_val;
2751 ret_val = e1000e_write_kmrn_reg(hw,
2754 if (ret_val)
2755 return ret_val;
2756 ret_val = e1000e_read_kmrn_reg(hw,
2759 if (ret_val)
2760 return ret_val;
2763 ret_val = e1000e_write_kmrn_reg(hw,
2766 if (ret_val)
2767 return ret_val;
2773 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2774 if (ret_val)
2775 return ret_val;
2778 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2779 if (ret_val)
2780 return ret_val;
2784 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2785 if (ret_val)
2786 return ret_val;
2787 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2788 if (ret_val)
2789 return ret_val;
2791 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2792 if (ret_val)
2793 return ret_val;
2804 ret_val = e1000e_read_kmrn_reg(hw,
2807 if (ret_val)
2808 return ret_val;
2809 ret_val = e1000e_write_kmrn_reg(hw,
2812 if (ret_val)
2813 return ret_val;
2814 ret_val = e1000e_read_kmrn_reg(hw,
2817 if (ret_val)
2818 return ret_val;
2821 ret_val = e1000e_write_kmrn_reg(hw,
2824 if (ret_val)
2825 return ret_val;
2830 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2831 if (ret_val)
2832 return ret_val;
2835 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2836 if (ret_val)
2837 return ret_val;
2841 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2842 if (ret_val)
2843 return ret_val;
2844 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2845 if (ret_val)
2846 return ret_val;
2848 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2849 if (ret_val)
2850 return ret_val;
2865 s32 ret_val = 0;
2871 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2872 if (ret_val)
2873 return ret_val;
2875 ret_val = hw->phy.ops.acquire(hw);
2876 if (ret_val)
2877 return ret_val;
2879 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2880 if (ret_val)
2883 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2887 return ret_val;
2899 s32 ret_val = 0;
2906 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2907 if (ret_val)
2908 return ret_val;
2917 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2918 if (ret_val)
2919 return ret_val;
2921 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2922 if (ret_val)
2923 return ret_val;
2934 return ret_val;
2999 s32 ret_val = 0;
3011 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3012 if (ret_val)
3013 return ret_val;
3016 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3017 if (ret_val)
3018 return ret_val;
3032 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3033 if (ret_val)
3034 return ret_val;
3037 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3047 ret_val = hw->phy.ops.acquire(hw);
3048 if (ret_val)
3049 return ret_val;
3050 ret_val = e1000_write_emi_reg_locked(hw,
3056 return ret_val;
3069 s32 ret_val = 0;
3076 ret_val = e1000e_phy_hw_reset_generic(hw);
3077 if (ret_val)
3078 return ret_val;
3096 s32 ret_val;
3099 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
3100 if (ret_val)
3101 return ret_val;
3131 s32 ret_val = 0;
3153 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3154 if (ret_val)
3155 return ret_val;
3157 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3158 if (ret_val)
3159 return ret_val;
3173 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3175 if (ret_val)
3176 return ret_val;
3179 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3181 if (ret_val)
3182 return ret_val;
3184 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3186 if (ret_val)
3187 return ret_val;
3190 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3192 if (ret_val)
3193 return ret_val;
3217 s32 ret_val = 0;
3235 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3237 if (ret_val)
3238 return ret_val;
3241 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3243 if (ret_val)
3244 return ret_val;
3246 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3248 if (ret_val)
3249 return ret_val;
3252 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3254 if (ret_val)
3255 return ret_val;
3273 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3274 if (ret_val)
3275 return ret_val;
3278 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3281 return ret_val;
3300 s32 ret_val;
3318 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3320 if (ret_val)
3321 return ret_val;
3330 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3333 if (ret_val)
3334 return ret_val;
3363 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3365 if (ret_val)
3366 return ret_val;
3374 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3377 if (ret_val)
3378 return ret_val;
3405 s32 ret_val = 0;
3414 ret_val = -E1000_ERR_NVM;
3420 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3421 if (ret_val) {
3429 ret_val = 0;
3439 ret_val =
3443 if (ret_val)
3454 ret_val =
3458 if (ret_val)
3477 if (ret_val)
3478 e_dbg("NVM read error: %d\n", ret_val);
3480 return ret_val;
3498 s32 ret_val = 0;
3505 ret_val = -E1000_ERR_NVM;
3511 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3512 if (ret_val) {
3520 ret_val = 0;
3525 ret_val = e1000_read_flash_word_ich8lan(hw,
3528 if (ret_val)
3537 if (ret_val)
3538 e_dbg("NVM read error: %d\n", ret_val);
3540 return ret_val;
3553 s32 ret_val = -E1000_ERR_NVM;
3589 ret_val = 0;
3599 ret_val = 0;
3604 if (!ret_val) {
3619 return ret_val;
3707 s32 ret_val;
3716 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3718 if (ret_val)
3719 return ret_val;
3742 s32 ret_val = -E1000_ERR_NVM;
3754 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3755 if (ret_val)
3766 ret_val =
3775 if (!ret_val) {
3799 return ret_val;
3817 s32 ret_val = -E1000_ERR_NVM;
3828 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3829 if (ret_val)
3845 ret_val =
3854 if (!ret_val) {
3874 return ret_val;
3927 s32 ret_val;
3930 ret_val = e1000e_update_nvm_checksum_generic(hw);
3931 if (ret_val)
3943 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3944 if (ret_val) {
3952 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3953 if (ret_val)
3958 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3959 if (ret_val)
3967 ret_val = e1000_read_flash_dword_ich8lan(hw,
3980 if (ret_val)
4000 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4002 if (ret_val)
4009 if (ret_val) {
4024 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4026 if (ret_val)
4030 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4032 if (ret_val)
4037 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4039 if (ret_val)
4043 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4045 if (ret_val)
4060 if (!ret_val) {
4066 if (ret_val)
4067 e_dbg("NVM update error: %d\n", ret_val);
4069 return ret_val;
4088 s32 ret_val;
4091 ret_val = e1000e_update_nvm_checksum_generic(hw);
4092 if (ret_val)
4104 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4105 if (ret_val) {
4113 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4114 if (ret_val)
4119 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4120 if (ret_val)
4127 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4130 if (ret_val)
4149 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4152 if (ret_val)
4156 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4159 if (ret_val)
4166 if (ret_val) {
4178 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4179 if (ret_val)
4183 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4186 if (ret_val)
4195 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4196 if (ret_val)
4211 if (!ret_val) {
4217 if (ret_val)
4218 e_dbg("NVM update error: %d\n", ret_val);
4220 return ret_val;
4233 s32 ret_val;
4262 ret_val = e1000_read_nvm(hw, word, 1, &data);
4263 if (ret_val)
4264 return ret_val;
4271 ret_val = e1000_write_nvm(hw, word, 1, &data);
4272 if (ret_val)
4273 return ret_val;
4274 ret_val = e1000e_update_nvm_checksum(hw);
4275 if (ret_val)
4276 return ret_val;
4341 s32 ret_val;
4358 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4359 if (ret_val)
4393 ret_val =
4396 if (!ret_val)
4414 return ret_val;
4431 s32 ret_val;
4443 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4444 if (ret_val)
4475 ret_val =
4479 if (!ret_val)
4498 return ret_val;
4529 s32 ret_val;
4534 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4536 if (!ret_val)
4537 return ret_val;
4541 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4542 if (!ret_val)
4563 s32 ret_val;
4566 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4567 if (!ret_val)
4568 return ret_val;
4573 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4574 if (!ret_val)
4599 s32 ret_val;
4648 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4649 if (ret_val)
4650 return ret_val;
4675 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4676 if (!ret_val)
4688 return ret_val;
4706 s32 ret_val;
4708 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4709 if (ret_val) {
4711 return ret_val;
4736 s32 ret_val;
4742 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4743 if (ret_val)
4744 return ret_val;
4802 s32 ret_val;
4804 ret_val = e1000e_get_bus_info_pcie(hw);
4814 return ret_val;
4829 s32 ret_val;
4834 ret_val = e1000e_disable_pcie_master(hw);
4835 if (ret_val)
4861 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4862 if (ret_val)
4863 return ret_val;
4887 ret_val = e1000_acquire_swflag_ich8lan(hw);
4901 if (!ret_val)
4905 ret_val = hw->phy.ops.get_cfg_done(hw);
4906 if (ret_val)
4907 return ret_val;
4909 ret_val = e1000_post_phy_reset_ich8lan(hw);
4910 if (ret_val)
4911 return ret_val;
4947 s32 ret_val;
4952 ret_val = hw->phy.ops.acquire(hw);
4953 if (ret_val)
4954 return ret_val;
4956 ret_val = e1000_reconfigure_k1_exit_timeout(hw);
4958 if (ret_val) {
4960 return ret_val;
4965 ret_val = mac->ops.id_led_init(hw);
4967 if (ret_val)
4986 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4987 if (ret_val)
4988 return ret_val;
4992 ret_val = mac->ops.setup_link(hw);
5037 return ret_val;
5129 s32 ret_val;
5154 ret_val = hw->mac.ops.setup_physical_interface(hw);
5155 if (ret_val)
5156 return ret_val;
5165 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5167 if (ret_val)
5168 return ret_val;
5185 s32 ret_val;
5197 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5198 if (ret_val)
5199 return ret_val;
5200 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5202 if (ret_val)
5203 return ret_val;
5205 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5207 if (ret_val)
5208 return ret_val;
5212 ret_val = e1000e_copper_link_setup_igp(hw);
5213 if (ret_val)
5214 return ret_val;
5218 ret_val = e1000e_copper_link_setup_m88(hw);
5219 if (ret_val)
5220 return ret_val;
5224 ret_val = e1000_copper_link_setup_82577(hw);
5225 if (ret_val)
5226 return ret_val;
5229 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5230 if (ret_val)
5231 return ret_val;
5247 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5248 if (ret_val)
5249 return ret_val;
5269 s32 ret_val;
5276 ret_val = e1000_copper_link_setup_82577(hw);
5277 if (ret_val)
5278 return ret_val;
5296 s32 ret_val;
5298 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5299 if (ret_val)
5300 return ret_val;
5304 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5307 return ret_val;
5329 s32 ret_val;
5340 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5346 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5347 if (ret_val)
5348 return ret_val;
5350 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5351 if (ret_val)
5352 return ret_val;
5461 s32 ret_val;
5467 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5469 if (ret_val)
5472 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5474 if (ret_val)
5498 s32 ret_val;
5516 ret_val = hw->phy.ops.acquire(hw);
5517 if (ret_val)
5523 ret_val =
5527 if (ret_val)
5600 ret_val = hw->phy.ops.acquire(hw);
5601 if (ret_val)
5620 s32 ret_val;
5625 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5626 if (ret_val) {
5627 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5639 ret_val = hw->phy.ops.acquire(hw);
5640 if (ret_val) {
5654 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5655 if (ret_val)
5664 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5665 if (ret_val)
5670 if (ret_val)
5671 e_dbg("Error %d in resume workarounds\n", ret_val);
5820 s32 ret_val = 0;
5830 ret_val = e1000e_get_auto_rd_done(hw);
5831 if (ret_val) {
5837 ret_val = 0;
5858 ret_val = -E1000_ERR_CONFIG;
5862 return ret_val;
5890 s32 ret_val;
5913 ret_val = hw->phy.ops.acquire(hw);
5914 if (ret_val)
5916 ret_val = hw->phy.ops.set_page(hw,
5918 if (ret_val)