Lines Matching full:phy
3 * drivers/net/ethernet/ibm/emac/phy.c
5 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
30 #include "phy.h"
35 static inline int _phy_read(struct mii_phy *phy, int reg)
37 return phy->mdio_read(phy->dev, phy->address, reg);
40 static inline void _phy_write(struct mii_phy *phy, int reg, int val)
42 phy->mdio_write(phy->dev, phy->address, reg, val);
45 static inline int gpcs_phy_read(struct mii_phy *phy, int reg)
47 return phy->mdio_read(phy->dev, phy->gpcs_address, reg);
50 static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val)
52 phy->mdio_write(phy->dev, phy->gpcs_address, reg, val);
55 int emac_mii_reset_phy(struct mii_phy *phy)
60 val = phy_read(phy, MII_BMCR);
63 phy_write(phy, MII_BMCR, val);
68 val = phy_read(phy, MII_BMCR);
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
79 int emac_mii_reset_gpcs(struct mii_phy *phy)
84 val = gpcs_phy_read(phy, MII_BMCR);
87 gpcs_phy_write(phy, MII_BMCR, val);
92 val = gpcs_phy_read(phy, MII_BMCR);
98 gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
100 if (limit > 0 && phy->mode == PHY_INTERFACE_MODE_SGMII) {
102 gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */
103 gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */
104 gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX */
110 static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
114 phy->autoneg = AUTONEG_ENABLE;
115 phy->speed = SPEED_10;
116 phy->duplex = DUPLEX_HALF;
117 phy->pause = phy->asym_pause = 0;
118 phy->advertising = advertise;
120 ctl = phy_read(phy, MII_BMCR);
125 /* First clear the PHY */
126 phy_write(phy, MII_BMCR, ctl);
129 adv = phy_read(phy, MII_ADVERTISE);
146 phy_write(phy, MII_ADVERTISE, adv);
148 if (phy->features &
150 adv = phy_read(phy, MII_CTRL1000);
158 phy_write(phy, MII_CTRL1000, adv);
162 ctl = phy_read(phy, MII_BMCR);
164 phy_write(phy, MII_BMCR, ctl);
169 static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
173 phy->autoneg = AUTONEG_DISABLE;
174 phy->speed = speed;
175 phy->duplex = fd;
176 phy->pause = phy->asym_pause = 0;
178 ctl = phy_read(phy, MII_BMCR);
183 /* First clear the PHY */
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
201 phy_write(phy, MII_BMCR, ctl);
206 static int genmii_poll_link(struct mii_phy *phy)
211 phy_read(phy, MII_BMSR);
212 status = phy_read(phy, MII_BMSR);
215 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
220 static int genmii_read_link(struct mii_phy *phy)
222 if (phy->autoneg == AUTONEG_ENABLE) {
224 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
228 if (phy->features &
230 int adv = phy_read(phy, MII_CTRL1000);
231 glpa = phy_read(phy, MII_STAT1000);
239 phy->speed = SPEED_10;
240 phy->duplex = DUPLEX_HALF;
241 phy->pause = phy->asym_pause = 0;
244 phy->speed = SPEED_1000;
246 phy->duplex = DUPLEX_FULL;
248 phy->speed = SPEED_100;
250 phy->duplex = DUPLEX_FULL;
252 phy->duplex = DUPLEX_FULL;
254 if (phy->duplex == DUPLEX_FULL) {
255 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
256 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
259 int bmcr = phy_read(phy, MII_BMCR);
264 phy->duplex = DUPLEX_FULL;
266 phy->duplex = DUPLEX_HALF;
268 phy->speed = SPEED_1000;
270 phy->speed = SPEED_100;
272 phy->speed = SPEED_10;
274 phy->pause = phy->asym_pause = 0;
306 static int cis8201_init(struct mii_phy *phy)
310 epcr = phy_read(phy, MII_CIS8201_EPCR);
316 switch (phy->mode) {
331 phy_write(phy, MII_CIS8201_EPCR, epcr);
334 phy_write(phy, MII_CIS8201_ACSR,
335 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
338 phy_write(phy, MII_CIS8201_10BTCSR,
339 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
367 static int m88e1111_init(struct mii_phy *phy)
370 phy_write(phy, 0x14, 0x0ce3);
371 phy_write(phy, 0x18, 0x4101);
372 phy_write(phy, 0x09, 0x0e00);
373 phy_write(phy, 0x04, 0x01e1);
374 phy_write(phy, 0x00, 0x9140);
375 phy_write(phy, 0x00, 0x1140);
380 static int m88e1112_init(struct mii_phy *phy)
383 * Marvell 88E1112 PHY needs to have the SGMII MAC
393 phy_write(phy, 0x16, 0x0002);
395 phy_write(phy, 0x00, 0x0040); /* 1Gbps */
396 reg_short = (u16)(phy_read(phy, 0x1a));
398 phy_write(phy, 0x1a, reg_short);
399 emac_mii_reset_phy(phy); /* reset MAC interface */
402 phy_write(phy, 0x16, 0x0000);
407 static int et1011c_init(struct mii_phy *phy)
411 reg_short = (u16)(phy_read(phy, 0x16));
414 phy_write(phy, 0x16, reg_short);
416 reg_short = (u16)(phy_read(phy, 0x17));
418 phy_write(phy, 0x17, reg_short);
420 phy_write(phy, 0x1c, 0x74f0);
474 static int ar8035_init(struct mii_phy *phy)
476 phy_write(phy, 0x1d, 0x5); /* Address debug register 5 */
477 phy_write(phy, 0x1e, 0x2d47); /* Value copied from u-boot */
478 phy_write(phy, 0x1d, 0xb); /* Address hib ctrl */
479 phy_write(phy, 0x1e, 0xbc20); /* Value copied from u-boot */
510 int emac_mii_phy_probe(struct mii_phy *phy, int address)
516 phy->autoneg = AUTONEG_DISABLE;
517 phy->advertising = 0;
518 phy->address = address;
519 phy->speed = SPEED_10;
520 phy->duplex = DUPLEX_HALF;
521 phy->pause = phy->asym_pause = 0;
523 /* Take PHY out of isolate mode and reset it. */
524 if (emac_mii_reset_phy(phy))
528 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
536 phy->def = def;
538 /* Determine PHY features if needed */
539 phy->features = def->features;
540 if (!phy->features) {
541 u16 bmsr = phy_read(phy, MII_BMSR);
543 phy->features |= SUPPORTED_Autoneg;
545 phy->features |= SUPPORTED_10baseT_Half;
547 phy->features |= SUPPORTED_10baseT_Full;
549 phy->features |= SUPPORTED_100baseT_Half;
551 phy->features |= SUPPORTED_100baseT_Full;
553 u16 esr = phy_read(phy, MII_ESTATUS);
555 phy->features |= SUPPORTED_1000baseT_Full;
557 phy->features |= SUPPORTED_1000baseT_Half;
559 phy->features |= SUPPORTED_MII;
563 phy->advertising = phy->features;