Lines Matching refs:dev
116 static inline void emac_report_timeout_error(struct emac_instance *dev,
119 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
122 DBG(dev, "%s" NL, error);
124 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error);
131 static inline void emac_rx_clk_tx(struct emac_instance *dev)
134 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
136 0, SDR0_MFR_ECS >> dev->cell_index);
140 static inline void emac_rx_clk_default(struct emac_instance *dev)
143 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
145 SDR0_MFR_ECS >> dev->cell_index, 0);
185 static void emac_clean_tx_ring(struct emac_instance *dev);
186 static void __emac_set_multicast_list(struct emac_instance *dev);
204 static inline void emac_tx_enable(struct emac_instance *dev)
206 struct emac_regs __iomem *p = dev->emacp;
209 DBG(dev, "tx_enable" NL);
216 static void emac_tx_disable(struct emac_instance *dev)
218 struct emac_regs __iomem *p = dev->emacp;
221 DBG(dev, "tx_disable" NL);
225 int n = dev->stop_timeout;
232 emac_report_timeout_error(dev, "TX disable timeout");
236 static void emac_rx_enable(struct emac_instance *dev)
238 struct emac_regs __iomem *p = dev->emacp;
241 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
244 DBG(dev, "rx_enable" NL);
250 int n = dev->stop_timeout;
256 emac_report_timeout_error(dev,
265 static void emac_rx_disable(struct emac_instance *dev)
267 struct emac_regs __iomem *p = dev->emacp;
270 DBG(dev, "rx_disable" NL);
274 int n = dev->stop_timeout;
281 emac_report_timeout_error(dev, "RX disable timeout");
285 static inline void emac_netif_stop(struct emac_instance *dev)
287 netif_tx_lock_bh(dev->ndev);
288 netif_addr_lock(dev->ndev);
289 dev->no_mcast = 1;
290 netif_addr_unlock(dev->ndev);
291 netif_tx_unlock_bh(dev->ndev);
292 netif_trans_update(dev->ndev); /* prevent tx timeout */
293 mal_poll_disable(dev->mal, &dev->commac);
294 netif_tx_disable(dev->ndev);
297 static inline void emac_netif_start(struct emac_instance *dev)
299 netif_tx_lock_bh(dev->ndev);
300 netif_addr_lock(dev->ndev);
301 dev->no_mcast = 0;
302 if (dev->mcast_pending && netif_running(dev->ndev))
303 __emac_set_multicast_list(dev);
304 netif_addr_unlock(dev->ndev);
305 netif_tx_unlock_bh(dev->ndev);
307 netif_wake_queue(dev->ndev);
314 mal_poll_enable(dev->mal, &dev->commac);
317 static inline void emac_rx_disable_async(struct emac_instance *dev)
319 struct emac_regs __iomem *p = dev->emacp;
322 DBG(dev, "rx_disable_async" NL);
329 static int emac_reset(struct emac_instance *dev)
331 struct emac_regs __iomem *p = dev->emacp;
335 DBG(dev, "reset" NL);
337 if (!dev->reset_failed) {
341 emac_rx_disable(dev);
342 emac_tx_disable(dev);
364 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
365 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
366 dev->phy_map == 0xffffffff)) {
369 0, SDR0_ETH_CFG_ECS << dev->cell_index);
373 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
383 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
391 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
392 dev->phy_map == 0xffffffff)) {
395 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
401 dev->reset_failed = 0;
404 emac_report_timeout_error(dev, "reset timeout");
405 dev->reset_failed = 1;
410 static void emac_hash_mc(struct emac_instance *dev)
412 u32 __iomem *gaht_base = emac_gaht_base(dev);
413 const int regs = EMAC_XAHT_REGS(dev);
418 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
422 netdev_for_each_mc_addr(ha, dev->ndev) {
424 DBG2(dev, "mc %pM" NL, ha->addr);
426 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
428 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
429 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
440 struct emac_instance *dev = netdev_priv(ndev);
445 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
453 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
458 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
466 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
470 DBG2(dev, "__emac_calc_base_mr1" NL);
478 dev->ndev->name, tx_size);
490 dev->ndev->name, rx_size);
496 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
499 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
501 DBG2(dev, "__emac4_calc_base_mr1" NL);
518 dev->ndev->name, tx_size);
536 dev->ndev->name, rx_size);
542 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
544 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
545 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
546 __emac_calc_base_mr1(dev, tx_size, rx_size);
549 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
551 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
557 static inline u32 emac_calc_rwmr(struct emac_instance *dev,
560 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
566 static int emac_configure(struct emac_instance *dev)
568 struct emac_regs __iomem *p = dev->emacp;
569 struct net_device *ndev = dev->ndev;
570 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
573 DBG(dev, "configure" NL);
579 } else if (emac_reset(dev) < 0)
582 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
583 tah_reset(dev->tah_dev);
585 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
586 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
589 tx_size = dev->tx_fifo_size;
590 rx_size = dev->rx_fifo_size;
597 else if (dev->phy.duplex == DUPLEX_FULL)
601 dev->stop_timeout = STOP_TIMEOUT_10;
602 switch (dev->phy.speed) {
604 if (emac_phy_gpcs(dev->phy.mode)) {
606 (dev->phy.gpcs_address != 0xffffffff) ?
607 dev->phy.gpcs_address : dev->phy.address);
617 tx_size = dev->tx_fifo_size_gige;
618 rx_size = dev->rx_fifo_size_gige;
620 if (dev->ndev->mtu > ETH_DATA_LEN) {
621 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
625 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
627 dev->stop_timeout = STOP_TIMEOUT_1000;
631 dev->stop_timeout = STOP_TIMEOUT_100;
637 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
638 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
639 dev->phy.speed);
640 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
641 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
646 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
647 dev->phy.duplex == DUPLEX_FULL) {
648 if (dev->phy.pause)
650 else if (dev->phy.asym_pause)
655 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
670 emac_hash_mc(dev);
674 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
675 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
676 tx_size / 2 / dev->fifo_entry_size);
678 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
679 tx_size / 2 / dev->fifo_entry_size);
681 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
702 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
703 rx_size / 4 / dev->fifo_entry_size);
713 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
719 if (emac_phy_gpcs(dev->phy.mode)) {
720 if (dev->phy.gpcs_address != 0xffffffff)
721 emac_mii_reset_gpcs(&dev->phy);
723 emac_mii_reset_phy(&dev->phy);
729 static void emac_reinitialize(struct emac_instance *dev)
731 DBG(dev, "reinitialize" NL);
733 emac_netif_stop(dev);
734 if (!emac_configure(dev)) {
735 emac_tx_enable(dev);
736 emac_rx_enable(dev);
738 emac_netif_start(dev);
741 static void emac_full_tx_reset(struct emac_instance *dev)
743 DBG(dev, "full_tx_reset" NL);
745 emac_tx_disable(dev);
746 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
747 emac_clean_tx_ring(dev);
748 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
750 emac_configure(dev);
752 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
753 emac_tx_enable(dev);
754 emac_rx_enable(dev);
759 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
761 DBG(dev, "reset_work" NL);
763 mutex_lock(&dev->link_lock);
764 if (dev->opened) {
765 emac_netif_stop(dev);
766 emac_full_tx_reset(dev);
767 emac_netif_start(dev);
769 mutex_unlock(&dev->link_lock);
774 struct emac_instance *dev = netdev_priv(ndev);
776 DBG(dev, "tx_timeout" NL);
778 schedule_work(&dev->reset_work);
782 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
786 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
792 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
794 struct emac_regs __iomem *p = dev->emacp;
798 mutex_lock(&dev->mdio_lock);
800 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
803 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
804 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
805 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
806 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
810 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
813 DBG2(dev, " -> timeout wait idle\n");
819 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
820 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
822 r = EMAC_STACR_BASE(dev->opb_bus_freq);
823 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
825 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
835 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
838 DBG2(dev, " -> timeout wait complete\n");
844 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
851 DBG2(dev, "mdio_read -> %04x" NL, r);
854 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
855 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
856 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
857 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
858 mutex_unlock(&dev->mdio_lock);
863 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
866 struct emac_regs __iomem *p = dev->emacp;
870 mutex_lock(&dev->mdio_lock);
872 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
875 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
876 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
877 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
878 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
882 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
885 DBG2(dev, " -> timeout wait idle\n");
891 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
892 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
894 r = EMAC_STACR_BASE(dev->opb_bus_freq);
895 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
897 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
908 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
911 DBG2(dev, " -> timeout wait complete\n");
916 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
917 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
918 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
919 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
920 mutex_unlock(&dev->mdio_lock);
925 struct emac_instance *dev = netdev_priv(ndev);
928 res = __emac_mdio_read((dev->mdio_instance &&
929 dev->phy.gpcs_address != id) ?
930 dev->mdio_instance : dev,
937 struct emac_instance *dev = netdev_priv(ndev);
939 __emac_mdio_write((dev->mdio_instance &&
940 dev->phy.gpcs_address != id) ?
941 dev->mdio_instance : dev,
946 static void __emac_set_multicast_list(struct emac_instance *dev)
948 struct emac_regs __iomem *p = dev->emacp;
949 u32 rmr = emac_iff2rmr(dev->ndev);
951 DBG(dev, "__multicast %08x" NL, rmr);
968 dev->mcast_pending = 0;
969 emac_rx_disable(dev);
971 emac_hash_mc(dev);
973 emac_rx_enable(dev);
979 struct emac_instance *dev = netdev_priv(ndev);
981 DBG(dev, "multicast" NL);
983 BUG_ON(!netif_running(dev->ndev));
985 if (dev->no_mcast) {
986 dev->mcast_pending = 1;
990 mutex_lock(&dev->link_lock);
991 __emac_set_multicast_list(dev);
992 mutex_unlock(&dev->link_lock);
997 struct emac_instance *dev = netdev_priv(ndev);
999 struct emac_regs __iomem *p = dev->emacp;
1004 mutex_lock(&dev->link_lock);
1008 emac_rx_disable(dev);
1009 emac_tx_disable(dev);
1014 emac_tx_enable(dev);
1015 emac_rx_enable(dev);
1017 mutex_unlock(&dev->link_lock);
1022 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
1029 mutex_lock(&dev->link_lock);
1030 emac_netif_stop(dev);
1031 emac_rx_disable(dev);
1032 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1034 if (dev->rx_sg_skb) {
1035 ++dev->estats.rx_dropped_resize;
1036 dev_kfree_skb(dev->rx_sg_skb);
1037 dev->rx_sg_skb = NULL;
1045 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
1046 ++dev->estats.rx_dropped_resize;
1048 dev->rx_desc[i].data_len = 0;
1049 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
1054 if (rx_skb_size <= dev->rx_skb_size)
1061 skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size);
1067 BUG_ON(!dev->rx_skb[i]);
1068 dev_kfree_skb(dev->rx_skb[i]);
1070 dev->rx_desc[i].data_ptr =
1071 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1074 dev->rx_skb[i] = skb;
1078 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1080 (dev->ndev->mtu > ETH_DATA_LEN);
1083 (dev->ndev->mtu > ETH_DATA_LEN);
1088 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1090 WRITE_ONCE(dev->ndev->mtu, new_mtu);
1091 emac_full_tx_reset(dev);
1094 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1097 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1098 dev->rx_slot = 0;
1099 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1100 emac_rx_enable(dev);
1101 emac_netif_start(dev);
1102 mutex_unlock(&dev->link_lock);
1110 struct emac_instance *dev = netdev_priv(ndev);
1113 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1118 ret = emac_resize_rx_ring(dev, new_mtu);
1123 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1124 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1130 static void emac_clean_tx_ring(struct emac_instance *dev)
1135 if (dev->tx_skb[i]) {
1136 dev_kfree_skb(dev->tx_skb[i]);
1137 dev->tx_skb[i] = NULL;
1138 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1139 ++dev->estats.tx_dropped;
1141 dev->tx_desc[i].ctrl = 0;
1142 dev->tx_desc[i].data_ptr = 0;
1146 static void emac_clean_rx_ring(struct emac_instance *dev)
1151 if (dev->rx_skb[i]) {
1152 dev->rx_desc[i].ctrl = 0;
1153 dev_kfree_skb(dev->rx_skb[i]);
1154 dev->rx_skb[i] = NULL;
1155 dev->rx_desc[i].data_ptr = 0;
1158 if (dev->rx_sg_skb) {
1159 dev_kfree_skb(dev->rx_sg_skb);
1160 dev->rx_sg_skb = NULL;
1165 __emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot)
1170 dev->rx_skb[slot] = skb;
1171 dev->rx_desc[slot].data_len = 0;
1173 dev->rx_desc[slot].data_ptr =
1174 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1175 dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN;
1177 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1184 emac_alloc_rx_skb(struct emac_instance *dev, int slot)
1188 skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size,
1191 return __emac_prepare_rx_skb(skb, dev, slot);
1195 emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot)
1199 skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size);
1201 return __emac_prepare_rx_skb(skb, dev, slot);
1204 static void emac_print_link_status(struct emac_instance *dev)
1206 if (netif_carrier_ok(dev->ndev))
1208 dev->ndev->name, dev->phy.speed,
1209 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1210 dev->phy.pause ? ", pause enabled" :
1211 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1213 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1219 struct emac_instance *dev = netdev_priv(ndev);
1222 DBG(dev, "open" NL);
1226 if (emac_alloc_rx_skb(dev, i)) {
1232 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1233 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1234 dev->rx_sg_skb = NULL;
1236 mutex_lock(&dev->link_lock);
1237 dev->opened = 1;
1241 if (dev->phy.address >= 0) {
1243 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1244 dev->phy.def->ops->read_link(&dev->phy);
1245 emac_rx_clk_default(dev);
1246 netif_carrier_on(dev->ndev);
1249 emac_rx_clk_tx(dev);
1250 netif_carrier_off(dev->ndev);
1253 dev->link_polling = 1;
1255 schedule_delayed_work(&dev->link_work, link_poll_interval);
1256 emac_print_link_status(dev);
1258 netif_carrier_on(dev->ndev);
1263 emac_configure(dev);
1264 mal_poll_add(dev->mal, &dev->commac);
1265 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1266 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1267 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1268 emac_tx_enable(dev);
1269 emac_rx_enable(dev);
1270 emac_netif_start(dev);
1272 mutex_unlock(&dev->link_lock);
1276 emac_clean_rx_ring(dev);
1282 static int emac_link_differs(struct emac_instance *dev)
1284 u32 r = in_be32(&dev->emacp->mr1);
1308 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1309 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1315 struct emac_instance *dev =
1320 mutex_lock(&dev->link_lock);
1321 DBG2(dev, "link timer" NL);
1323 if (!dev->opened)
1326 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1327 if (!netif_carrier_ok(dev->ndev)) {
1328 emac_rx_clk_default(dev);
1330 dev->phy.def->ops->read_link(&dev->phy);
1332 netif_carrier_on(dev->ndev);
1333 emac_netif_stop(dev);
1334 emac_full_tx_reset(dev);
1335 emac_netif_start(dev);
1336 emac_print_link_status(dev);
1340 if (netif_carrier_ok(dev->ndev)) {
1341 emac_rx_clk_tx(dev);
1342 netif_carrier_off(dev->ndev);
1343 netif_tx_disable(dev->ndev);
1344 emac_reinitialize(dev);
1345 emac_print_link_status(dev);
1349 schedule_delayed_work(&dev->link_work, link_poll_interval);
1351 mutex_unlock(&dev->link_lock);
1354 static void emac_force_link_update(struct emac_instance *dev)
1356 netif_carrier_off(dev->ndev);
1358 if (dev->link_polling) {
1359 cancel_delayed_work_sync(&dev->link_work);
1360 if (dev->link_polling)
1361 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1368 struct emac_instance *dev = netdev_priv(ndev);
1370 DBG(dev, "close" NL);
1372 if (dev->phy.address >= 0) {
1373 dev->link_polling = 0;
1374 cancel_delayed_work_sync(&dev->link_work);
1376 mutex_lock(&dev->link_lock);
1377 emac_netif_stop(dev);
1378 dev->opened = 0;
1379 mutex_unlock(&dev->link_lock);
1381 emac_rx_disable(dev);
1382 emac_tx_disable(dev);
1383 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1384 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1385 mal_poll_del(dev->mal, &dev->commac);
1387 emac_clean_tx_ring(dev);
1388 emac_clean_rx_ring(dev);
1395 static inline u16 emac_tx_csum(struct emac_instance *dev,
1398 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1400 ++dev->stats.tx_packets_csum;
1406 static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len)
1408 struct emac_regs __iomem *p = dev->emacp;
1409 struct net_device *ndev = dev->ndev;
1412 * difference, then we can store the TMR0 value in "dev"
1415 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1420 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1422 DBG2(dev, "stopped TX queue" NL);
1426 ++dev->stats.tx_packets;
1427 dev->stats.tx_bytes += len;
1435 struct emac_instance *dev = netdev_priv(ndev);
1440 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1442 slot = dev->tx_slot++;
1443 if (dev->tx_slot == NUM_TX_BUFF) {
1444 dev->tx_slot = 0;
1448 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1450 dev->tx_skb[slot] = skb;
1451 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1454 dev->tx_desc[slot].data_len = (u16) len;
1456 dev->tx_desc[slot].ctrl = ctrl;
1458 return emac_xmit_finish(dev, len);
1461 static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1476 dev->tx_skb[slot] = NULL;
1477 dev->tx_desc[slot].data_ptr = pd;
1478 dev->tx_desc[slot].data_len = (u16) chunk;
1479 dev->tx_desc[slot].ctrl = ctrl;
1480 ++dev->tx_cnt;
1494 struct emac_instance *dev = netdev_priv(ndev);
1511 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1515 emac_tx_csum(dev, skb);
1516 slot = dev->tx_slot;
1519 dev->tx_skb[slot] = NULL;
1521 dev->tx_desc[slot].data_ptr = pd =
1522 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1523 dev->tx_desc[slot].data_len = (u16) chunk;
1526 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1533 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1536 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1539 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1543 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1546 dev->tx_skb[slot] = skb;
1549 if (dev->tx_slot == NUM_TX_BUFF - 1)
1552 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1553 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1555 return emac_xmit_finish(dev, skb->len);
1561 while (slot != dev->tx_slot) {
1562 dev->tx_desc[slot].ctrl = 0;
1563 --dev->tx_cnt;
1567 ++dev->estats.tx_undo;
1571 DBG2(dev, "stopped TX queue" NL);
1576 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1578 struct emac_error_stats *st = &dev->estats;
1580 DBG(dev, "BD TX error %04x" NL, ctrl);
1605 struct emac_instance *dev = param;
1608 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1610 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1615 netif_tx_lock_bh(dev->ndev);
1616 if (dev->tx_cnt) {
1618 int slot = dev->ack_slot, n = 0;
1620 ctrl = dev->tx_desc[slot].ctrl;
1622 struct sk_buff *skb = dev->tx_skb[slot];
1627 dev->tx_skb[slot] = NULL;
1632 emac_parse_tx_error(dev, ctrl);
1634 if (--dev->tx_cnt)
1638 dev->ack_slot = slot;
1639 if (netif_queue_stopped(dev->ndev) &&
1640 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1641 netif_wake_queue(dev->ndev);
1643 DBG2(dev, "tx %d pkts" NL, n);
1646 netif_tx_unlock_bh(dev->ndev);
1649 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1652 struct sk_buff *skb = dev->rx_skb[slot];
1654 DBG2(dev, "recycle %d %d" NL, slot, len);
1657 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1661 dev->rx_desc[slot].data_len = 0;
1663 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1667 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1669 struct emac_error_stats *st = &dev->estats;
1671 DBG(dev, "BD RX error %04x" NL, ctrl);
1694 static inline void emac_rx_csum(struct emac_instance *dev,
1698 if (!ctrl && dev->tah_dev) {
1700 ++dev->stats.rx_packets_csum;
1705 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1707 if (likely(dev->rx_sg_skb != NULL)) {
1708 int len = dev->rx_desc[slot].data_len;
1709 int tot_len = dev->rx_sg_skb->len + len;
1711 if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) {
1712 ++dev->estats.rx_dropped_mtu;
1713 dev_kfree_skb(dev->rx_sg_skb);
1714 dev->rx_sg_skb = NULL;
1716 memcpy(skb_tail_pointer(dev->rx_sg_skb),
1717 dev->rx_skb[slot]->data, len);
1718 skb_put(dev->rx_sg_skb, len);
1719 emac_recycle_rx_skb(dev, slot, len);
1723 emac_recycle_rx_skb(dev, slot, 0);
1731 struct emac_instance *dev = param;
1732 int slot = dev->rx_slot, received = 0;
1734 DBG2(dev, "poll_rx(%d)" NL, budget);
1740 u16 ctrl = dev->rx_desc[slot].ctrl;
1745 skb = dev->rx_skb[slot];
1747 len = dev->rx_desc[slot].data_len;
1754 emac_parse_rx_error(dev, ctrl);
1755 ++dev->estats.rx_dropped_error;
1756 emac_recycle_rx_skb(dev, slot, 0);
1762 ++dev->estats.rx_dropped_stack;
1763 emac_recycle_rx_skb(dev, slot, len);
1770 copy_skb = napi_alloc_skb(&dev->mal->napi, len);
1777 emac_recycle_rx_skb(dev, slot, len);
1779 } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot)))
1784 skb->protocol = eth_type_trans(skb, dev->ndev);
1785 emac_rx_csum(dev, skb, ctrl);
1789 ++dev->stats.rx_packets;
1791 dev->stats.rx_bytes += len;
1798 BUG_ON(dev->rx_sg_skb);
1799 if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) {
1800 DBG(dev, "rx OOM %d" NL, slot);
1801 ++dev->estats.rx_dropped_oom;
1802 emac_recycle_rx_skb(dev, slot, 0);
1804 dev->rx_sg_skb = skb;
1807 } else if (!emac_rx_sg_append(dev, slot) &&
1810 skb = dev->rx_sg_skb;
1811 dev->rx_sg_skb = NULL;
1815 emac_parse_rx_error(dev, ctrl);
1816 ++dev->estats.rx_dropped_error;
1824 DBG(dev, "rx OOM %d" NL, slot);
1826 ++dev->estats.rx_dropped_oom;
1827 emac_recycle_rx_skb(dev, slot, 0);
1834 DBG2(dev, "rx %d BDs" NL, received);
1835 dev->rx_slot = slot;
1838 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1840 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1841 DBG2(dev, "rx restart" NL);
1846 if (dev->rx_sg_skb) {
1847 DBG2(dev, "dropping partial rx packet" NL);
1848 ++dev->estats.rx_dropped_error;
1849 dev_kfree_skb(dev->rx_sg_skb);
1850 dev->rx_sg_skb = NULL;
1853 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1854 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1855 emac_rx_enable(dev);
1856 dev->rx_slot = 0;
1864 struct emac_instance *dev = param;
1866 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1872 struct emac_instance *dev = param;
1874 int slot = dev->rx_slot;
1876 u16 ctrl = dev->rx_desc[slot].ctrl;
1885 if (unlikely(slot == dev->rx_slot))
1893 struct emac_instance *dev = param;
1895 ++dev->estats.rx_stopped;
1896 emac_rx_disable_async(dev);
1902 struct emac_instance *dev = dev_instance;
1903 struct emac_regs __iomem *p = dev->emacp;
1904 struct emac_error_stats *st = &dev->estats;
1907 spin_lock(&dev->lock);
1912 DBG(dev, "isr = %08x" NL, isr);
1945 spin_unlock(&dev->lock);
1952 struct emac_instance *dev = netdev_priv(ndev);
1953 struct emac_stats *st = &dev->stats;
1954 struct emac_error_stats *est = &dev->estats;
1958 DBG2(dev, "stats" NL);
1961 spin_lock_irqsave(&dev->lock, flags);
1999 spin_unlock_irqrestore(&dev->lock, flags);
2021 struct emac_instance *dev = netdev_priv(ndev);
2024 supported = dev->phy.features;
2026 cmd->base.phy_address = dev->phy.address;
2028 mutex_lock(&dev->link_lock);
2029 advertising = dev->phy.advertising;
2030 cmd->base.autoneg = dev->phy.autoneg;
2031 cmd->base.speed = dev->phy.speed;
2032 cmd->base.duplex = dev->phy.duplex;
2033 mutex_unlock(&dev->link_lock);
2047 struct emac_instance *dev = netdev_priv(ndev);
2048 u32 f = dev->phy.features;
2054 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
2058 if (dev->phy.address < 0)
2098 mutex_lock(&dev->link_lock);
2099 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed,
2101 mutex_unlock(&dev->link_lock);
2107 mutex_lock(&dev->link_lock);
2108 dev->phy.def->ops->setup_aneg(&dev->phy,
2110 (dev->phy.advertising &
2113 mutex_unlock(&dev->link_lock);
2115 emac_force_link_update(dev);
2133 struct emac_instance *dev = netdev_priv(ndev);
2135 mutex_lock(&dev->link_lock);
2136 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2137 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2140 if (dev->phy.duplex == DUPLEX_FULL) {
2141 if (dev->phy.pause)
2143 else if (dev->phy.asym_pause)
2146 mutex_unlock(&dev->link_lock);
2149 static int emac_get_regs_len(struct emac_instance *dev)
2157 struct emac_instance *dev = netdev_priv(ndev);
2161 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2162 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2163 size += zmii_get_regs_len(dev->zmii_dev);
2164 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2165 size += rgmii_get_regs_len(dev->rgmii_dev);
2166 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2167 size += tah_get_regs_len(dev->tah_dev);
2172 static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2176 hdr->index = dev->cell_index;
2177 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2179 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2184 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs));
2191 struct emac_instance *dev = netdev_priv(ndev);
2197 buf = mal_dump_regs(dev->mal, buf);
2198 buf = emac_dump_regs(dev, buf);
2199 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2201 buf = zmii_dump_regs(dev->zmii_dev, buf);
2203 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2205 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2207 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2209 buf = tah_dump_regs(dev->tah_dev, buf);
2215 struct emac_instance *dev = netdev_priv(ndev);
2218 DBG(dev, "nway_reset" NL);
2220 if (dev->phy.address < 0)
2223 mutex_lock(&dev->link_lock);
2224 if (!dev->phy.autoneg) {
2229 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2231 mutex_unlock(&dev->link_lock);
2232 emac_force_link_update(dev);
2255 struct emac_instance *dev = netdev_priv(ndev);
2257 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2258 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2259 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2265 struct emac_instance *dev = netdev_priv(ndev);
2270 dev->cell_index, dev->ofdev->dev.of_node);
2295 struct emac_instance *dev = netdev_priv(ndev);
2298 DBG(dev, "ioctl %08x" NL, cmd);
2300 if (dev->phy.address < 0)
2305 data->phy_id = dev->phy.address;
2308 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2313 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2336 static int emac_check_deps(struct emac_instance *dev,
2350 np = *(dev->blist - 1);
2377 static void emac_put_deps(struct emac_instance *dev)
2379 platform_device_put(dev->mal_dev);
2380 platform_device_put(dev->zmii_dev);
2381 platform_device_put(dev->rgmii_dev);
2382 platform_device_put(dev->mdio_dev);
2383 platform_device_put(dev->tah_dev);
2386 static int emac_wait_deps(struct emac_instance *dev)
2393 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2394 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2395 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2396 if (dev->tah_ph)
2397 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2398 if (dev->mdio_ph)
2399 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2400 if (dev->blist && dev->blist > emac_boot_list)
2402 err = emac_check_deps(dev, deps);
2409 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2410 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2411 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2412 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2413 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2435 struct emac_instance *dev = netdev_priv(ndev);
2438 dev->phy.autoneg = phy->autoneg;
2439 dev->phy.speed = phy->speed;
2440 dev->phy.duplex = phy->duplex;
2441 dev->phy.pause = phy->pause;
2442 dev->phy.asym_pause = phy->asym_pause;
2443 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising,
2468 struct emac_instance *dev = netdev_priv(bus->priv);
2470 return emac_reset(dev);
2486 struct net_device *ndev = phy->dev;
2495 struct net_device *ndev = phy->dev;
2505 struct net_device *ndev = phy->dev;
2506 struct emac_instance *dev = netdev_priv(ndev);
2511 dev_err(&dev->ofdev->dev, "link update failed (%d).", res);
2520 struct net_device *ndev = phy->dev;
2537 struct net_device *ndev = phy->dev;
2551 static int emac_dt_mdio_probe(struct emac_instance *dev)
2557 mii_np = of_get_available_child_by_name(dev->ofdev->dev.of_node, "mdio");
2559 dev_err(&dev->ofdev->dev, "no mdio definition found.");
2563 bus = devm_mdiobus_alloc(&dev->ofdev->dev);
2569 bus->priv = dev->ndev;
2570 bus->parent = dev->ndev->dev.parent;
2575 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name);
2576 res = devm_of_mdiobus_register(&dev->ofdev->dev, bus, mii_np);
2578 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)",
2587 static int emac_dt_phy_connect(struct emac_instance *dev,
2592 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
2594 if (!dev->phy.def)
2597 phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link, 0,
2598 dev->phy_mode);
2600 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n");
2604 dev->phy.def->phy_id = phy_dev->drv->phy_id;
2605 dev->phy.def->phy_id_mask = phy_dev->drv->phy_id_mask;
2606 dev->phy.def->name = phy_dev->drv->name;
2607 dev->phy.def->ops = &emac_dt_mdio_phy_ops;
2608 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features,
2610 dev->phy.address = phy_dev->mdio.addr;
2611 dev->phy.mode = phy_dev->interface;
2615 static int emac_dt_phy_probe(struct emac_instance *dev)
2617 struct device_node *np = dev->ofdev->dev.of_node;
2624 res = emac_dt_mdio_probe(dev);
2626 res = emac_dt_phy_connect(dev, phy_handle);
2634 static int emac_init_phy(struct emac_instance *dev)
2636 struct device_node *np = dev->ofdev->dev.of_node;
2637 struct net_device *ndev = dev->ndev;
2641 dev->phy.dev = ndev;
2642 dev->phy.mode = dev->phy_mode;
2645 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) ||
2647 emac_reset(dev);
2650 dev->phy.address = -1;
2651 dev->phy.features = SUPPORTED_MII;
2652 if (emac_phy_supports_gige(dev->phy_mode))
2653 dev->phy.features |= SUPPORTED_1000baseT_Full;
2655 dev->phy.features |= SUPPORTED_100baseT_Full;
2656 dev->phy.pause = 1;
2659 int res = emac_dt_mdio_probe(dev);
2668 emac_adjust_link(dev->ndev);
2669 put_device(&ndev->phydev->mdio.dev);
2675 phy_map = dev->phy_map | busy_phy_map;
2677 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2679 dev->phy.mdio_read = emac_mdio_read;
2680 dev->phy.mdio_write = emac_mdio_write;
2684 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2688 emac_rx_clk_tx(dev);
2692 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2698 if (emac_phy_gpcs(dev->phy.mode)) {
2707 dev->phy.gpcs_address = dev->gpcs_address;
2708 if (dev->phy.gpcs_address == 0xffffffff)
2709 dev->phy.address = dev->cell_index;
2712 emac_configure(dev);
2714 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2715 int res = emac_dt_phy_probe(dev);
2731 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
2737 if (dev->phy_address != 0xffffffff)
2738 phy_map = ~(1 << dev->phy_address);
2746 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2749 if (!emac_mii_phy_probe(&dev->phy, i))
2755 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2766 if (dev->phy.def->ops->init)
2767 dev->phy.def->ops->init(&dev->phy);
2770 dev->phy.def->features &= ~dev->phy_feat_exc;
2771 dev->phy.features &= ~dev->phy_feat_exc;
2774 if (dev->phy.features & SUPPORTED_Autoneg) {
2775 adv = dev->phy.features;
2776 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2779 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2781 u32 f = dev->phy.def->features;
2799 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2804 static int emac_init_config(struct emac_instance *dev)
2806 struct device_node *np = dev->ofdev->dev.of_node;
2810 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2812 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2814 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2816 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2818 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2819 dev->max_mtu = ETH_DATA_LEN;
2820 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2821 dev->rx_fifo_size = 2048;
2822 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2823 dev->tx_fifo_size = 2048;
2824 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2825 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2826 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2827 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2828 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2829 dev->phy_address = 0xffffffff;
2830 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2831 dev->phy_map = 0xffffffff;
2832 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2833 dev->gpcs_address = 0xffffffff;
2834 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2836 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2837 dev->tah_ph = 0;
2838 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2839 dev->tah_port = 0;
2840 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2841 dev->mdio_ph = 0;
2842 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2843 dev->zmii_ph = 0;
2844 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2845 dev->zmii_port = 0xffffffff;
2846 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2847 dev->rgmii_ph = 0;
2848 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2849 dev->rgmii_port = 0xffffffff;
2850 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2851 dev->fifo_entry_size = 16;
2852 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2853 dev->mal_burst_size = 256;
2856 err = of_get_phy_mode(np, &dev->phy_mode);
2858 dev->phy_mode = PHY_INTERFACE_MODE_NA;
2862 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2865 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2868 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2870 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2875 dev->features |= EMAC_FTR_EMAC4;
2877 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2881 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2884 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2896 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2898 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2902 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2906 if (dev->tah_ph != 0) {
2908 dev->features |= EMAC_FTR_HAS_TAH;
2915 if (dev->zmii_ph != 0) {
2917 dev->features |= EMAC_FTR_HAS_ZMII;
2924 if (dev->rgmii_ph != 0) {
2926 dev->features |= EMAC_FTR_HAS_RGMII;
2934 err = of_get_ethdev_address(np, dev->ndev);
2938 dev_warn(&dev->ofdev->dev, "Can't get valid mac-address. Generating random.");
2939 eth_hw_addr_random(dev->ndev);
2943 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2944 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2945 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2947 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2948 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2952 if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS))
2955 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2956 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2957 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2958 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2959 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2992 struct emac_instance *dev;
2993 struct device_node *np = ofdev->dev.of_node;
3011 ndev = devm_alloc_etherdev(&ofdev->dev, sizeof(struct emac_instance));
3015 dev = netdev_priv(ndev);
3016 dev->ndev = ndev;
3017 dev->ofdev = ofdev;
3018 dev->blist = blist;
3019 SET_NETDEV_DEV(ndev, &ofdev->dev);
3022 err = devm_mutex_init(&ofdev->dev, &dev->mdio_lock);
3026 err = devm_mutex_init(&ofdev->dev, &dev->link_lock);
3030 spin_lock_init(&dev->lock);
3031 INIT_WORK(&dev->reset_work, emac_reset_work);
3034 err = emac_init_config(dev);
3039 dev->emac_irq = platform_get_irq(ofdev, 0);
3040 err = devm_request_irq(&ofdev->dev, dev->emac_irq, emac_irq, 0, "EMAC",
3041 dev);
3043 dev_err_probe(&ofdev->dev, err, "failed to request IRQ %d",
3044 dev->emac_irq);
3048 ndev->irq = dev->emac_irq;
3050 dev->emacp = devm_platform_ioremap_resource(ofdev, 0);
3051 if (IS_ERR(dev->emacp)) {
3052 dev_err(&ofdev->dev, "can't map device registers");
3053 err = PTR_ERR(dev->emacp);
3058 err = emac_wait_deps(dev);
3061 dev->mal = platform_get_drvdata(dev->mal_dev);
3062 if (dev->mdio_dev != NULL)
3063 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev);
3066 dev->commac.ops = &emac_commac_ops;
3067 dev->commac.dev = dev;
3068 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
3069 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
3070 err = mal_register_commac(dev->mal, &dev->commac);
3073 np, dev->mal_dev->dev.of_node);
3076 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
3077 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
3080 dev->tx_desc =
3081 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
3082 dev->rx_desc =
3083 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
3085 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
3086 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
3089 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
3090 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
3091 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
3092 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
3095 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
3096 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
3100 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
3101 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
3105 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
3106 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
3110 dev->phy.speed = SPEED_100;
3111 dev->phy.duplex = DUPLEX_FULL;
3112 dev->phy.autoneg = AUTONEG_DISABLE;
3113 dev->phy.pause = dev->phy.asym_pause = 0;
3114 dev->stop_timeout = STOP_TIMEOUT_100;
3115 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
3118 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
3119 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
3125 err = emac_init_phy(dev);
3129 if (dev->tah_dev) {
3134 if (emac_phy_supports_gige(dev->phy_mode)) {
3136 dev->commac.ops = &emac_commac_sg_ops;
3143 ndev->max_mtu = dev->max_mtu;
3147 err = devm_register_netdev(&ofdev->dev, ndev);
3158 platform_set_drvdata(ofdev, dev);
3161 ndev->name, dev->cell_index, np, ndev->dev_addr);
3163 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII)
3166 if (dev->phy.address >= 0)
3168 dev->phy.def->name, dev->phy.address);
3176 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3177 tah_detach(dev->tah_dev, dev->tah_port);
3179 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3180 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3182 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3183 zmii_detach(dev->zmii_dev, dev->zmii_port);
3185 mal_unregister_commac(dev->mal, &dev->commac);
3187 emac_put_deps(dev);
3196 struct emac_instance *dev = platform_get_drvdata(ofdev);
3198 DBG(dev, "remove" NL);
3200 cancel_work_sync(&dev->reset_work);
3202 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3203 tah_detach(dev->tah_dev, dev->tah_port);
3204 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3205 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3206 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3207 zmii_detach(dev->zmii_dev, dev->zmii_port);
3209 busy_phy_map &= ~(1 << dev->phy.address);
3210 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
3212 mal_unregister_commac(dev->mal, &dev->commac);
3213 emac_put_deps(dev);