Lines Matching full:phy

62 /* PHY module I2C device address */
68 /* PHY transceiver type */
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
90 			err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr,
93 			err = t3_mdio_change_bits(phy, rv->mmd_addr,
100 static void ael100x_txon(struct cphy *phy)
103 		phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
106 	t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
111  * Read an 8-bit word from a device attached to the PHY's i2c bus.
113 static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
118 	err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
125 		err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
129 			err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
136 	CH_WARN(phy->adapter, "PHY %u i2c read of dev.addr %#x.%#x timed out\n",
137 		phy->mdio.prtad, dev_addr, word_addr);
141 static int ael1002_power_down(struct cphy *phy, int enable)
145 	err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
147 		err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
153 static int ael1002_reset(struct cphy *phy, int wait)
157 	if ((err = ael1002_power_down(phy, 0)) ||
158 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
159 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
160 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
161 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
162 	    (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
168 static int ael1002_intr_noop(struct cphy *phy)
176 static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed,
181 		int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
185 			err = t3_mdio_read(phy, MDIO_MMD_PCS,
188 			err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
212 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
215 	cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops,
218 	ael100x_txon(phy);
222 static int ael1006_reset(struct cphy *phy, int wait)
224 	return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait);
238 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
241 	cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops,
244 	ael100x_txon(phy);
251 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms)
259 	v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);
270 	v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);
276 	v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);
281 		v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
291  * Code to support the Aeluros/NetLogic 2005 10Gb PHY.
293 static int ael2005_setup_sr_edc(struct cphy *phy)
304 	err = set_phy_regs(phy, regs);
310 	if (phy->priv != edc_sr)
311 		err = t3_get_edc_fw(phy, EDC_OPT_AEL2005,
317 		err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
318 				    phy->phy_cache[i],
319 				    phy->phy_cache[i + 1]);
321 		phy->priv = edc_sr;
325 static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
338 	err = set_phy_regs(phy, regs);
340 		err = set_phy_regs(phy, preemphasis);
346 	if (phy->priv != edc_twinax)
347 		err = t3_get_edc_fw(phy, EDC_TWX_AEL2005,
353 		err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
354 				    phy->phy_cache[i],
355 				    phy->phy_cache[i + 1]);
357 		phy->priv = edc_twinax;
361 static int ael2005_get_module_type(struct cphy *phy, int delay_ms)
366 	v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
373 	return ael2xxx_get_module_type(phy, delay_ms);
376 static int ael2005_intr_enable(struct cphy *phy)
378 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
379 	return err ? err : t3_phy_lasi_intr_enable(phy);
382 static int ael2005_intr_disable(struct cphy *phy)
384 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
385 	return err ? err : t3_phy_lasi_intr_disable(phy);
388 static int ael2005_intr_clear(struct cphy *phy)
390 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
391 	return err ? err : t3_phy_lasi_intr_clear(phy);
394 static int ael2005_reset(struct cphy *phy, int wait)
415 	err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
420 	err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
425 	phy->priv = edc_none;
426 	err = set_phy_regs(phy, regs0);
432 	err = ael2005_get_module_type(phy, 0);
435 	phy->modtype = err;
438 		err = ael2005_setup_twinax_edc(phy, err);
440 		err = ael2005_setup_sr_edc(phy);
444 	err = set_phy_regs(phy, regs1);
450 		err = ael2005_intr_enable(phy);
454 static int ael2005_intr_handler(struct cphy *phy)
459 	ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat);
464 		ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL,
470 		ret = ael2005_get_module_type(phy, 300);
474 		phy->modtype = ret;
476 			edc_needed = phy->priv;       /* on unplug retain EDC */
483 		if (edc_needed != phy->priv) {
484 			ret = ael2005_reset(phy, 0);
490 	ret = t3_phy_lasi_intr_handler(phy);
509 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
512 	cphy_init(phy, adapter, phy_addr, &ael2005_ops, mdio_ops,
516 	return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,
523 static int ael2020_setup_sr_edc(struct cphy *phy)
539 	err = set_phy_regs(phy, regs);
544 	phy->priv = edc_sr;
551 static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
575 	err = set_phy_regs(phy, uCclock40MHz);
579 	err = set_phy_regs(phy, uCclockActivate);
584 	if (phy->priv != edc_twinax)
585 		err = t3_get_edc_fw(phy, EDC_TWX_AEL2020,
591 		err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
592 				    phy->phy_cache[i],
593 				    phy->phy_cache[i + 1]);
595 	err = set_phy_regs(phy, uCactivate);
597 		phy->priv = edc_twinax;
604 static int ael2020_get_module_type(struct cphy *phy, int delay_ms)
609 	v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat);
618 	return ael2xxx_get_module_type(phy, delay_ms);
622  * Enable PHY interrupts.  We enable "Module Detection" interrupts (on any
625 static int ael2020_intr_enable(struct cphy *phy)
644 	err = set_phy_regs(phy, regs);
648 	err = get_link_status_r(phy, &link_ok, NULL, NULL, NULL);
652 		t3_link_changed(phy->adapter,
653 				phy2portid(phy));
655 	err = t3_phy_lasi_intr_enable(phy);
663  * Disable PHY interrupts.  The mirror of the above ...
665 static int ael2020_intr_disable(struct cphy *phy)
682 	err = set_phy_regs(phy, regs);
686 	return t3_phy_lasi_intr_disable(phy);
690  * Clear PHY interrupt state.
692 static int ael2020_intr_clear(struct cphy *phy)
700 	int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
701 	return err ? err : t3_phy_lasi_intr_clear(phy);
720  * Reset the PHY and put it into a canonical operating state.
722 static int ael2020_reset(struct cphy *phy, int wait)
728 	err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
733 	err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125);
739 	phy->priv = edc_none;
740 	err = set_phy_regs(phy, ael2020_reset_regs);
745 	err = ael2020_get_module_type(phy, 0);
748 	phy->modtype = (u8)err;
750 		err = ael2020_setup_twinax_edc(phy, err);
752 		err = ael2020_setup_sr_edc(phy);
758 		err = ael2005_intr_enable(phy);
763  * Handle a PHY interrupt.
765 static int ael2020_intr_handler(struct cphy *phy)
770 	ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
776 		ret = ael2020_get_module_type(phy, 300);
780 		phy->modtype = (u8)ret;
782 			edc_needed = phy->priv;       /* on unplug retain EDC */
789 		if (edc_needed != phy->priv) {
790 			ret = ael2020_reset(phy, 0);
796 	ret = t3_phy_lasi_intr_handler(phy);
815 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
818 	cphy_init(phy, adapter, phy_addr, &ael2020_ops, mdio_ops,
823 	return set_phy_regs(phy, ael2020_reset_regs);
829 static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed,
834 		int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
838 			err = t3_mdio_read(phy, MDIO_MMD_PCS,
841 			err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
865 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
870 	cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops,
875 	 * Some cards where the PHY is supposed to be at address 0 actually
879 	    !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) &&
881 		phy->mdio.prtad = 1;
885 static int xaui_direct_reset(struct cphy *phy, int wait)
890 static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
895 		int prtad = phy->mdio.prtad;
897 		status = t3_read_reg(phy->adapter,
899 		    t3_read_reg(phy->adapter,
901 		    t3_read_reg(phy->adapter,
903 		    t3_read_reg(phy->adapter,
914 static int xaui_direct_power_down(struct cphy *phy, int enable)
929 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
932 	cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops,