chelsio/cxgb/subr.c

41  *	@adapter: the adapter performing the operation
52 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
56 		u32 val = readl(adapter->regs + reg) & mask;
72 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
76 	writel(addr, adapter->regs + A_TPI_ADDR);
77 	writel(value, adapter->regs + A_TPI_WR_DATA);
78 	writel(F_TPIWR, adapter->regs + A_TPI_CSR);
80 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
84 			 adapter->name, addr);
88 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
92 	spin_lock(&adapter->tpi_lock);
93 	ret = __t1_tpi_write(adapter, addr, value);
94 	spin_unlock(&adapter->tpi_lock);
101 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
105 	writel(addr, adapter->regs + A_TPI_ADDR);
106 	writel(0, adapter->regs + A_TPI_CSR);
108 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
112 			 adapter->name, addr);
114 		*valp = readl(adapter->regs + A_TPI_RD_DATA);
118 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
122 	spin_lock(&adapter->tpi_lock);
123 	ret = __t1_tpi_read(adapter, addr, valp);
124 	spin_unlock(&adapter->tpi_lock);
131 static void t1_tpi_par(adapter_t *adapter, u32 value)
133 	writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
141 void t1_link_changed(adapter_t *adapter, int port_id)
144 	struct cphy *phy = adapter->port[port_id].phy;
145 	struct link_config *lc = &adapter->port[port_id].link_config;
156 		struct cmac *mac = adapter->port[port_id].mac;
161 	t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
164 static bool t1_pci_intr_handler(adapter_t *adapter)
168 	pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
171 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
174 		t1_interrupts_disable(adapter);
175 		adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR;
176 		pr_alert("%s: PCI error encountered.\n", adapter->name);
188 static int fpga_phy_intr_handler(adapter_t *adapter)
191 	u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
193 	for_each_port(adapter, p)
195 			struct cphy *phy = adapter->port[p].phy;
199 				t1_link_changed(adapter, p);
201 	writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
208 static irqreturn_t fpga_slow_intr(adapter_t *adapter)
210 	u32 cause = readl(adapter->regs + A_PL_CAUSE);
215 		if (t1_sge_intr_error_handler(adapter->sge))
220 		fpga_phy_intr_handler(adapter);
227 		u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
230 		writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
233 		if (t1_pci_intr_handler(adapter))
239 		writel(cause, adapter->regs + A_PL_CAUSE);
251 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
258 		__t1_tpi_read(adapter, mi1_reg, &val);
264 		pr_alert("%s: MDIO operation timed out\n", adapter->name);
271 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
279 	t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
289 	struct adapter *adapter = dev->ml_priv;
293 	spin_lock(&adapter->tpi_lock);
294 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
295 	__t1_tpi_write(adapter,
297 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
298 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
299 	spin_unlock(&adapter->tpi_lock);
306 	struct adapter *adapter = dev->ml_priv;
309 	spin_lock(&adapter->tpi_lock);
310 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
311 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
312 	__t1_tpi_write(adapter,
314 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
315 	spin_unlock(&adapter->tpi_lock);
331 	struct adapter *adapter = dev->ml_priv;
335 	spin_lock(&adapter->tpi_lock);
338 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
339 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
340 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
342 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
345 	__t1_tpi_write(adapter,
347 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
350 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
351 	spin_unlock(&adapter->tpi_lock);
358 	struct adapter *adapter = dev->ml_priv;
361 	spin_lock(&adapter->tpi_lock);
364 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
365 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
366 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
368 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
371 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
372 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
373 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
374 	spin_unlock(&adapter->tpi_lock);
565 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
574 	pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
577 		pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
582 		       adapter->name, addr);
585 	pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
590 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
595 		ret = t1_seeprom_read(adapter, addr,
604 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
608 	if (t1_eeprom_vpd_get(adapter, &vpd))
634 				   (mac->adapter->params.nports < 2)))
670 int t1_elmer0_ext_intr_handler(adapter_t *adapter)
676 	t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
678 	switch (board_info(adapter)->board) {
685 		for_each_port(adapter, i) {
690 			phy = adapter->port[i].phy;
693 				t1_link_changed(adapter, i);
699 			phy = adapter->port[0].phy;
702 				t1_link_changed(adapter, 0);
713 		for_each_port(adapter, p) {
714 			phy = adapter->port[p].phy;
717 			    t1_link_changed(adapter, p);
726 			phy = adapter->port[0].phy;
729 				t1_link_changed(adapter, 0);
734 		if (netif_msg_intr(adapter))
735 			dev_dbg(&adapter->pdev->dev,
738 			struct cmac *mac = adapter->port[0].mac;
745 			t1_tpi_read(adapter,
747 			if (netif_msg_link(adapter))
748 				dev_info(&adapter->pdev->dev, "XPAK %s\n",
753 	t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
758 void t1_interrupts_enable(adapter_t *adapter)
762 	adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
764 	t1_sge_intr_enable(adapter->sge);
765 	t1_tp_intr_enable(adapter->tp);
766 	if (adapter->espi) {
767 		adapter->slow_intr_mask |= F_PL_INTR_ESPI;
768 		t1_espi_intr_enable(adapter->espi);
772 	for_each_port(adapter, i) {
773 		adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
774 		adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
778 	if (t1_is_asic(adapter)) {
779 		u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
782 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
785 		adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
787 		writel(pl_intr, adapter->regs + A_PL_ENABLE);
792 void t1_interrupts_disable(adapter_t* adapter)
796 	t1_sge_intr_disable(adapter->sge);
797 	t1_tp_intr_disable(adapter->tp);
798 	if (adapter->espi)
799 		t1_espi_intr_disable(adapter->espi);
802 	for_each_port(adapter, i) {
803 		adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
804 		adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
808 	if (t1_is_asic(adapter))
809 		writel(0, adapter->regs + A_PL_ENABLE);
812 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
814 	adapter->slow_intr_mask = 0;
818 void t1_interrupts_clear(adapter_t* adapter)
822 	t1_sge_intr_clear(adapter->sge);
823 	t1_tp_intr_clear(adapter->tp);
824 	if (adapter->espi)
825 		t1_espi_intr_clear(adapter->espi);
828 	for_each_port(adapter, i) {
829 		adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
830 		adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
834 	if (t1_is_asic(adapter)) {
835 		u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
838 		       adapter->regs + A_PL_CAUSE);
842 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
848 static irqreturn_t asic_slow_intr(adapter_t *adapter)
850 	u32 cause = readl(adapter->regs + A_PL_CAUSE);
853 	cause &= adapter->slow_intr_mask;
857 		if (t1_sge_intr_error_handler(adapter->sge))
861 		t1_tp_intr_handler(adapter->tp);
863 		t1_espi_intr_handler(adapter->espi);
865 		if (t1_pci_intr_handler(adapter))
873 		adapter->pending_thread_intr |= F_PL_INTR_EXT;
874 		adapter->slow_intr_mask &= ~F_PL_INTR_EXT;
875 		writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
876 		       adapter->regs + A_PL_ENABLE);
881 	writel(cause, adapter->regs + A_PL_CAUSE);
882 	readl(adapter->regs + A_PL_CAUSE); /* flush writes */
886 irqreturn_t t1_slow_intr_handler(adapter_t *adapter)
889 	if (!t1_is_asic(adapter))
890 		return fpga_slow_intr(adapter);
892 	return asic_slow_intr(adapter);
896 static void power_sequence_xpak(adapter_t* adapter)
902 	t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
905 		t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
907 		t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
911 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
919 		u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
937 static int board_init(adapter_t *adapter, const struct board_info *bi)
944 		t1_tpi_par(adapter, 0xf);
945 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
948 		t1_tpi_par(adapter, 0xf);
949 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
954 		power_sequence_xpak(adapter);
962 		t1_tpi_par(adapter, 0xf);
963 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
967 		t1_tpi_par(adapter, 0xf);
968 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
979 int t1_init_hw_modules(adapter_t *adapter)
982 	const struct board_info *bi = board_info(adapter);
985 		u32 val = readl(adapter->regs + A_MC4_CFG);
987 		writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
989 		       adapter->regs + A_MC5_CONFIG);
992 	if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
996 	if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
999 	err = t1_sge_configure(adapter->sge, &adapter->params.sge);
1011 static void get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
1016 	pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1025 void t1_free_sw_modules(adapter_t *adapter)
1029 	for_each_port(adapter, i) {
1030 		struct cmac *mac = adapter->port[i].mac;
1031 		struct cphy *phy = adapter->port[i].phy;
1039 	if (adapter->sge)
1040 		t1_sge_destroy(adapter->sge);
1041 	if (adapter->tp)
1042 		t1_tp_destroy(adapter->tp);
1043 	if (adapter->espi)
1044 		t1_espi_destroy(adapter->espi);
1068 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi)
1072 	adapter->params.brd_info = bi;
1073 	adapter->params.nports = bi->port_number;
1074 	adapter->params.stats_update_period = bi->gmac->stats_update_period;
1076 	adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1077 	if (!adapter->sge) {
1079 		       adapter->name);
1083 	if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1085 		       adapter->name);
1089 	adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1090 	if (!adapter->tp) {
1092 		       adapter->name);
1096 	board_init(adapter, bi);
1097 	bi->mdio_ops->init(adapter, bi);
1099 		bi->gphy->reset(adapter);
1101 		bi->gmac->reset(adapter);
1103 	for_each_port(adapter, i) {
1108 		adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,
1110 		if (!adapter->port[i].phy) {
1112 			       adapter->name, i);
1116 		adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1119 			       adapter->name, i);
1127 		if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1129 		else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1131 			       adapter->port[i].dev->name);
1134 		eth_hw_addr_set(adapter->port[i].dev, hw_addr);
1135 		init_link_config(&adapter->port[i].link_config, bi);
1138 	get_pci_mode(adapter, &adapter->params.pci);
1139 	t1_interrupts_clear(adapter);
1143 	t1_free_sw_modules(adapter);