Lines Matching full:adapter
35 adapter_t *adapter;
51 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
61 adapter->regs + A_ESPI_CMD_ADDR);
62 writel(0, adapter->regs + A_ESPI_GOSTAT);
65 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
69 pr_err("%s: TRICN write timed out\n", adapter->name);
74 static int tricn_init(adapter_t *adapter)
78 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
79 pr_err("%s: ESPI clock not ready\n", adapter->name);
83 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
86 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
87 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
88 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
91 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
93 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
95 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
96 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
97 tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
98 tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
99 tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
100 tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
103 adapter->regs + A_ESPI_RX_RESET);
110 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
119 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
120 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
121 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
126 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
127 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
128 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
133 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
135 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
136 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
141 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
160 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
167 if (status && t1_is_T1B(espi->adapter))
169 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
178 static void espi_setup_for_pm3393(adapter_t *adapter)
180 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
182 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
183 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
184 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
185 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
186 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
187 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
188 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
189 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
190 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
193 static void espi_setup_for_vsc7321(adapter_t *adapter)
195 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
196 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);
197 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
198 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
199 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
200 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
201 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG);
203 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
209 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
211 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
213 if (is_T2(adapter)) {
214 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
215 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
217 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
218 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
221 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
222 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
224 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG);
231 adapter_t *adapter = espi->adapter;
234 writel(0, adapter->regs + A_ESPI_TRAIN);
236 if (is_T2(adapter)) {
239 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
241 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
243 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
246 espi_setup_for_pm3393(adapter);
248 espi_setup_for_vsc7321(adapter);
251 espi_setup_for_ixf1010(adapter, nports);
256 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
258 if (is_T2(adapter)) {
259 tricn_init(adapter);
264 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL);
267 if (adapter->params.nports == 1)
269 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
281 struct peespi *t1_espi_create(adapter_t *adapter)
286 espi->adapter = adapter;
291 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
293 struct peespi *espi = adapter->espi;
295 if (!is_T2(adapter))
300 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
305 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
307 struct peespi *espi = adapter->espi;
310 if (!is_T2(adapter))
322 adapter->regs + A_ESPI_MISC_CONTROL);
323 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
324 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
326 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
336 int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
338 struct peespi *espi = adapter->espi;
339 u8 i, nport = (u8)adapter->params.nports;
350 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
355 adapter->regs + A_ESPI_MISC_CONTROL);
357 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
360 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);