Lines Matching refs:tw32
621 #define tw32(reg, val) tp->write32(tp, reg, val)
1002 tw32(TG3PCI_MISC_HOST_CTRL,
1015 tw32(TG3PCI_MISC_HOST_CTRL,
1032 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1034 tw32(HOSTCC_MODE, tp->coal_now);
1079 tw32(HOSTCC_MODE, tp->coalesce_mode |
1438 tw32(MAC_PHYCFG2, val);
1444 tw32(MAC_PHYCFG1, val);
1457 tw32(MAC_PHYCFG2, val);
1470 tw32(MAC_PHYCFG1, val);
1491 tw32(MAC_EXT_RGMII_MODE, val);
2050 tw32(MAC_MI_STAT,
2054 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2058 tw32(MAC_TX_LENGTHS,
2063 tw32(MAC_TX_LENGTHS,
2403 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2418 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2438 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2663 tw32(TG3_CPMU_CTRL,
2675 tw32(TG3_CPMU_CTRL, cpmuctrl);
2804 tw32(TG3_CPMU_DRV_STATUS, status);
3070 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3071 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3137 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3144 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3170 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3180 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3196 tw32(GRC_EEPROM_ADDR,
3230 tw32(NVRAM_CMD, nvram_cmd);
3299 tw32(NVRAM_ADDR, offset);
3343 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3346 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3350 tw32(GRC_EEPROM_ADDR, val |
3424 tw32(NVRAM_ADDR, phy_addr);
3443 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3445 tw32(NVRAM_ADDR, phy_addr + j);
3482 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3501 tw32(NVRAM_ADDR, phy_addr);
3548 tw32(NVRAM_WRITE1, 0x406);
3551 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3562 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3588 tw32(cpu_base + CPU_STATE, 0xffffffff);
3589 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3604 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3620 tw32(cpu_base + CPU_STATE, 0xffffffff);
3640 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3664 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3729 tw32(cpu_base + CPU_STATE, 0xffffffff);
3730 tw32(cpu_base + CPU_MODE,
3767 tw32(cpu_base + CPU_STATE, 0xffffffff);
3773 tw32(cpu_base + CPU_STATE, 0xffffffff);
3774 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3957 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3958 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3961 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3962 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3991 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4036 tw32(TG3PCI_MISC_HOST_CTRL,
4109 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4166 tw32(MAC_LED_CTRL, tp->led_ctrl);
4252 tw32(0x7d00, val);
4351 tw32(TG3_CPMU_EEE_MODE,
4718 tw32(MAC_EVENT, 0);
5008 tw32(MAC_LED_CTRL, led_ctrl);
5220 tw32(MAC_TX_AUTO_NEG, 0);
5249 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5264 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5777 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
6078 tw32(GRC_MISC_CFG, val);
6091 tw32(MAC_TX_LENGTHS, val |
6094 tw32(MAC_TX_LENGTHS, val |
6099 tw32(HOSTCC_STAT_COAL_TICKS,
6102 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6113 tw32(PCIE_PWR_MGMT_THRESH, val);
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6185 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6190 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6280 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6281 tw32(TG3_EAV_WATCHDOG0_MSB,
6285 tw32(TG3_EAV_REF_CLCK_CTL,
6288 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6289 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
7296 tw32(HOSTCC_MODE, tp->coalesce_mode |
8287 tw32(MAC_MODE, tp->mac_mode);
8378 tw32(MAC_MODE, mac_mode);
9027 tw32(FTQ_RESET, 0xffffffff);
9028 tw32(FTQ_RESET, 0x00000000);
9105 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
9117 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9123 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9138 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9145 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9182 tw32(GRC_FASTBOOT_PC, 0);
9221 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9233 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9236 tw32(GRC_MISC_CFG, (1 << 29));
9242 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9243 tw32(GRC_VCPU_EXT_CTRL,
9258 tw32(GRC_MISC_CFG, val);
9330 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9334 tw32(0x5000, 0x400);
9351 tw32(GRC_MODE, tp->grc_mode);
9356 tw32(0xc4, val | (1 << 15));
9364 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9389 tw32(0x7c00, val | (1 << 25));
9399 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9534 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9535 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9536 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9538 tw32(HOSTCC_TXCOL_TICKS, 0);
9539 tw32(HOSTCC_TXMAX_FRAMES, 0);
9540 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9546 tw32(reg, ec->tx_coalesce_usecs);
9548 tw32(reg, ec->tx_max_coalesced_frames);
9550 tw32(reg, ec->tx_max_coalesced_frames_irq);
9555 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9556 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9557 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9567 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9568 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9569 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9572 tw32(HOSTCC_RXCOL_TICKS, 0);
9573 tw32(HOSTCC_RXMAX_FRAMES, 0);
9574 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9581 tw32(reg, ec->rx_coalesce_usecs);
9583 tw32(reg, ec->rx_max_coalesced_frames);
9585 tw32(reg, ec->rx_max_coalesced_frames_irq);
9589 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9590 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9591 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9603 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9604 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9609 tw32(HOSTCC_STAT_COAL_TICKS, val);
9750 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9752 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9759 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9760 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9791 tw32(RCVBDI_STD_THRESH, val);
9794 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9804 tw32(RCVBDI_JUMBO_THRESH, val);
9807 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9818 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9819 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9820 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9821 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9865 tw32(MAC_HASH_REG_0, mc_filter[0]);
9866 tw32(MAC_HASH_REG_1, mc_filter[1]);
9867 tw32(MAC_HASH_REG_2, mc_filter[2]);
9868 tw32(MAC_HASH_REG_3, mc_filter[3]);
9934 tw32(reg, val);
9986 tw32(TG3_CPMU_CTRL, val);
9991 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9996 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
10001 tw32(TG3_CPMU_HST_ACC, val);
10008 tw32(PCIE_PWR_MGMT_THRESH, val);
10011 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
10013 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
10016 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
10024 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
10027 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
10030 tw32(GRC_MODE, grc_mode);
10039 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
10043 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
10046 tw32(GRC_MODE, grc_mode);
10055 tw32(TG3_CPMU_PADRNG_CTL, val);
10061 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
10066 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
10069 tw32(GRC_MODE, grc_mode);
10075 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
10093 tw32(TG3PCI_PCISTATE, val);
10104 tw32(TG3PCI_PCISTATE, val);
10111 tw32(TG3PCI_MSI_DATA, val);
10132 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10138 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10157 tw32(TG3_RX_PTP_CTL,
10163 tw32(GRC_MODE, tp->grc_mode | val);
10172 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
10179 tw32(GRC_MISC_CFG, val);
10185 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10187 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10189 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10190 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10191 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10197 tw32(BUFMGR_MB_POOL_ADDR,
10199 tw32(BUFMGR_MB_POOL_SIZE,
10204 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10206 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10208 tw32(BUFMGR_MB_HIGH_WATER,
10211 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10213 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10215 tw32(BUFMGR_MB_HIGH_WATER,
10218 tw32(BUFMGR_DMA_LOW_WATER,
10220 tw32(BUFMGR_DMA_HIGH_WATER,
10231 tw32(BUFMGR_MODE, val);
10243 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10264 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10266 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10269 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10274 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10284 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10286 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10290 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10295 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10298 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10311 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10326 tw32(MAC_RX_MTU_SIZE,
10342 tw32(MAC_TX_LENGTHS, val);
10345 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10346 tw32(RCVLPC_CONFIG, 0x0181);
10424 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10438 tw32(tgtreg, val |
10447 tw32(RCVLPC_STATS_ENABLE, val);
10452 tw32(RCVLPC_STATS_ENABLE, val);
10454 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10456 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10457 tw32(SNDDATAI_STATSENAB, 0xffffff);
10458 tw32(SNDDATAI_STATSCTRL,
10463 tw32(HOSTCC_MODE, 0);
10477 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10479 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10481 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10483 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10494 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10496 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10497 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10499 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10558 tw32(MSGINT_MODE, val);
10622 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10627 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10629 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10632 tw32(SNDDATAC_MODE,
10635 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10637 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10638 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10642 tw32(RCVDBDI_MODE, val);
10643 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10647 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10651 tw32(SNDBDI_MODE, val);
10652 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10697 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10718 tw32(MAC_LED_CTRL, tp->led_ctrl);
10720 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10736 tw32(MAC_SERDES_CFG, val);
10739 tw32(MAC_SERDES_CFG, 0x616000);
10762 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10765 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10792 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10793 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10794 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10795 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10805 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10808 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10811 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10814 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10817 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10820 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10823 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10826 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10829 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10832 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10835 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10838 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10841 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10843 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10875 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
11001 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
11030 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
11089 tw32(GRC_LOCAL_CTRL,
11092 tw32(HOSTCC_MODE, tp->coalesce_mode |
11383 tw32(MSGINT_MODE, val);
11429 tw32(MSGINT_MODE, val);
11627 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11725 tw32(PCIE_TRANSACTION_CFG,
12129 tw32(TG3_CPMU_CTRL, cpmu_val &
12193 tw32(TG3_CPMU_CTRL, cpmu_val);
12886 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12896 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12901 tw32(MAC_LED_CTRL, tp->led_ctrl);
13361 tw32(offset, 0);
13373 tw32(offset, read_mask | write_mask);
13385 tw32(offset, save_val);
13394 tw32(offset, save_val);
13544 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13761 tw32(i, 0x0);
14004 tw32(TG3_RX_PTP_CTL,
14488 tw32(NVRAM_CFG1, nvcfg1);
14594 tw32(NVRAM_CFG1, nvcfg1);
14670 tw32(NVRAM_CFG1, nvcfg1);
14788 tw32(NVRAM_CFG1, nvcfg1);
14861 tw32(NVRAM_CFG1, nvcfg1);
14978 tw32(NVRAM_CFG1, nvcfg1);
15502 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15503 tw32(OTP_CTRL, cmd);
15524 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15529 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15536 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
16709 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16906 tw32(GRC_MODE, val | tp->grc_mode);
16911 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16914 tw32(TG3PCI_REG_BASE_ADDR, 0);
17285 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17286 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17287 tw32(RDMAC_STATUS, 0);
17288 tw32(WDMAC_STATUS, 0);
17290 tw32(BUFMGR_MODE, 0);
17291 tw32(FTQ_RESET, 0);
17334 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17336 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17452 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17464 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17498 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17529 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17986 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);