broadcom/bnx2x/bnx2x_main.c

503 	opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
856 	int port = BP_PORT(bp);
1470 			TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1475 			TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1566 	int port = BP_PORT(bp);
2346 			   USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2543 	 *      abs_func = 2 * vn + BP_PORT + BP_PATH
2548 	 *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2553 		int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2641 		storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2714 		bp->link_params.port = BP_PORT(bp);
2954 		REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2982 	int port = BP_PORT(bp);
3341 		storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3354 	int port = BP_PORT(bp);
3363 	int port = BP_PORT(bp);
3564 	storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
4016 	int port = BP_PORT(bp);
4138 	int port = BP_PORT(bp);
4163 	int port = BP_PORT(bp);
4216 		int port = BP_PORT(bp);
4260 		int port = BP_PORT(bp);
5027 	int port = BP_PORT(bp);
5114 	int port = BP_PORT(bp);
6041 	int port = BP_PORT(bp);
6540 				       bp->common.shmem2_base, BP_PORT(bp));
6565 		REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
7000 	    (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
7514 	int port = BP_PORT(bp);
7579 		REG_WR(bp, (BP_PORT(bp) ?
7587 			REG_WR(bp, BP_PORT(bp) ?
7590 			REG_WR(bp, BP_PORT(bp) ?
7593 			REG_WR(bp, BP_PORT(bp) ?
7601 			REG_WR(bp, BP_PORT(bp) ?
7680 			REG_WR(bp, BP_PORT(bp) ?
7684 			REG_WR(bp, BP_PORT(bp) ?
7690 			REG_WR(bp, BP_PORT(bp) ?
7714 			REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7812 	int port = BP_PORT(bp);
7846 	int rc, i, port = BP_PORT(bp);
7952 	int port = BP_PORT(bp);
8228 				BP_PORT(bp) * (main_mem_size * 4);
8984 	int port = BP_PORT(bp);
9065 	int port = BP_PORT(bp);
9148 	int port = BP_PORT(bp);
9295 	int port = BP_PORT(bp);
9337 	int port = BP_PORT(bp);
9512 		int port = BP_PORT(bp);
9612 		offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9657 			val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10430 	u8 port = BP_PORT(bp);
10443 			base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10464 		vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10471 			base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10527 		addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10539 		       BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10626 	val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10670 	tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10874 			       (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
11018 	    (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11022 				     lfa_host_addr[BP_PORT(bp)]));
11090 			dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11186 	int cfg_size = 0, idx, port = BP_PORT(bp);
11494 	int port = BP_PORT(bp);
11579 	int port = BP_PORT(bp);
11663 	int port = BP_PORT(bp);
11745 	int port = BP_PORT(bp);
11837 	int port = BP_PORT(bp);
11900 		tmp = BP_PORT(bp);
11997 		bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
12182 			u8 other_port = !BP_PORT(bp);
12382 	    SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
14749 			int port = BP_PORT(bp);
14851 	offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
15077 		offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15104 	int port = BP_PORT(bp);
15156 	int port = BP_PORT(bp);
15181 	int port = BP_PORT(bp);
15271 	int port = BP_PORT(bp);
15383 	int rc, port = BP_PORT(bp);