Lines Matching refs:params
33 struct link_params *params,
215 static int bnx2x_check_half_open_conn(struct link_params *params,
218 struct link_params *params);
242 * @params: link parameters
246 static int bnx2x_check_lfa(struct link_params *params)
251 struct bnx2x *bp = params->bp;
254 REG_RD(bp, params->lfa_base +
262 REG_WR(bp, params->lfa_base +
269 link_status = REG_RD(bp, params->shmem_base +
271 port_mb[params->port].link_status));
278 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
282 if (params->loopback_mode)
286 if (!params->lfa_base)
289 if (params->num_phys == 3) {
298 saved_val = REG_RD(bp, params->lfa_base +
300 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
307 saved_val = REG_RD(bp, params->lfa_base +
309 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
316 saved_val = REG_RD(bp, params->lfa_base +
318 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
330 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
333 params->speed_cap_mask[cfg_idx]);
339 REG_RD(bp, params->lfa_base +
343 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
345 cur_req_fc_auto_adv, params->req_fc_auto_adv);
349 eee_status = REG_RD(bp, params->shmem2_base +
351 eee_status[params->port]));
354 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
356 (params->eee_mode & EEE_MODE_ADV_LPI))) {
357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
440 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
443 struct bnx2x *bp = params->bp;
531 const struct link_params *params,
534 struct bnx2x *bp = params->bp;
535 const u8 port = params->port;
569 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
572 struct bnx2x *bp = params->bp;
573 const u8 port = params->port;
645 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
653 const struct link_params *params,
656 struct bnx2x *bp = params->bp;
659 const u8 port = params->port;
686 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
688 struct bnx2x *bp = params->bp;
689 const u8 port = params->port;
737 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
744 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
747 struct bnx2x *bp = params->bp;
755 bnx2x_ets_e3b0_nig_disabled(params, vars);
757 bnx2x_ets_e3b0_pbf_disabled(params);
767 int bnx2x_ets_disabled(struct link_params *params,
770 struct bnx2x *bp = params->bp;
774 bnx2x_ets_e2e3a0_disabled(params);
776 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
790 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
795 struct bnx2x *bp = params->bp;
796 const u8 port = params->port;
893 const struct link_params *params,
897 struct bnx2x *bp = params->bp;
906 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
912 ets_params->cos[cos_idx].params.bw_params.bw
916 ets_params->cos[cos_idx].params.bw_params.bw;
953 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
957 struct bnx2x *bp = params->bp;
958 const u8 port = params->port;
1035 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1038 struct bnx2x *bp = params->bp;
1040 const u8 port = params->port;
1128 int bnx2x_ets_e3b0_config(const struct link_params *params,
1132 struct bnx2x *bp = params->bp;
1134 const u8 port = params->port;
1161 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1172 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1173 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1185 ets_params->cos[cos_entry].params.bw_params.bw,
1192 params,
1194 ets_params->cos[cos_entry].params.sp_params.pri,
1210 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1220 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1230 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1233 struct bnx2x *bp = params->bp;
1274 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1278 struct bnx2x *bp = params->bp;
1297 bnx2x_ets_bw_limit_common(params);
1306 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1309 struct bnx2x *bp = params->bp;
1349 static void bnx2x_update_pfc_xmac(struct link_params *params,
1353 struct bnx2x *bp = params->bp;
1358 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1366 if (!(params->feature_config_flags &
1399 ((params->mac_addr[2] << 24) |
1400 (params->mac_addr[3] << 16) |
1401 (params->mac_addr[4] << 8) |
1402 (params->mac_addr[5])));
1404 ((params->mac_addr[0] << 8) |
1405 (params->mac_addr[1])));
1444 struct link_params *params)
1448 for (phy_index = INT_PHY; phy_index < params->num_phys;
1450 bnx2x_set_mdio_clk(bp, params->chip_id,
1451 params->phy[phy_index].mdio_ctrl);
1467 static void bnx2x_emac_init(struct link_params *params,
1471 struct bnx2x *bp = params->bp;
1472 u8 port = params->port;
1499 bnx2x_set_mdio_emac_per_phy(bp, params);
1501 val = ((params->mac_addr[0] << 8) |
1502 params->mac_addr[1]);
1505 val = ((params->mac_addr[2] << 24) |
1506 (params->mac_addr[3] << 16) |
1507 (params->mac_addr[4] << 8) |
1508 params->mac_addr[5]);
1512 static void bnx2x_set_xumac_nig(struct link_params *params,
1516 struct bnx2x *bp = params->bp;
1518 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1520 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1526 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1528 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1530 struct bnx2x *bp = params->bp;
1532 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1545 static void bnx2x_umac_enable(struct link_params *params,
1549 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1550 struct bnx2x *bp = params->bp;
1553 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1557 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1562 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1610 ((params->mac_addr[2] << 24) |
1611 (params->mac_addr[3] << 16) |
1612 (params->mac_addr[4] << 8) |
1613 (params->mac_addr[5])));
1615 ((params->mac_addr[0] << 8) |
1616 (params->mac_addr[1])));
1637 bnx2x_set_xumac_nig(params,
1644 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1646 struct bnx2x *bp = params->bp;
1706 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1708 u8 port = params->port;
1709 struct bnx2x *bp = params->bp;
1734 static int bnx2x_xmac_enable(struct link_params *params,
1738 struct bnx2x *bp = params->bp;
1741 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1743 bnx2x_xmac_init(params, vars->line_speed);
1752 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1757 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1773 bnx2x_update_pfc_xmac(params, vars, 0);
1788 (params->phy[INT_PHY].supported &
1796 bnx2x_set_xumac_nig(params,
1804 static int bnx2x_emac_enable(struct link_params *params,
1807 struct bnx2x *bp = params->bp;
1808 u8 port = params->port;
1823 u32 ser_lane = ((params->lane_config &
1851 if (!(params->feature_config_flags &
1879 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1923 if ((params->feature_config_flags &
1937 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1941 struct bnx2x *bp = params->bp;
1942 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1946 if ((!(params->feature_config_flags &
1957 if (!(params->feature_config_flags &
1966 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1974 struct bnx2x *bp = params->bp;
1975 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1979 if ((!(params->feature_config_flags &
1991 if (!(params->feature_config_flags &
1999 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2028 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2043 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2099 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2101 struct bnx2x *bp = params->bp;
2103 REG_WR(bp, params->shmem_base +
2105 port_mb[params->port].link_status), link_status);
2108 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2110 struct bnx2x *bp = params->bp;
2113 REG_WR(bp, params->shmem2_base +
2115 link_attr_sync[params->port]), link_attr);
2118 static void bnx2x_update_pfc_nig(struct link_params *params,
2125 struct bnx2x *bp = params->bp;
2126 u8 port = params->port;
2128 int set_pfc = params->feature_config_flags &
2138 /* NIG params will override non PFC params, since it's possible to
2214 int bnx2x_update_pfc(struct link_params *params,
2223 struct bnx2x *bp = params->bp;
2224 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2226 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2231 bnx2x_update_mng(params, vars->link_status);
2233 /* Update NIG params */
2234 bnx2x_update_pfc_nig(params, vars, pfc_params);
2243 bnx2x_update_pfc_xmac(params, vars, 0);
2247 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2250 bnx2x_emac_enable(params, vars, 0);
2254 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2256 bnx2x_update_pfc_bmac1(params, vars);
2259 if ((params->feature_config_flags &
2263 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2268 static int bnx2x_bmac1_enable(struct link_params *params,
2272 struct bnx2x *bp = params->bp;
2273 u8 port = params->port;
2288 wb_data[0] = ((params->mac_addr[2] << 24) |
2289 (params->mac_addr[3] << 16) |
2290 (params->mac_addr[4] << 8) |
2291 params->mac_addr[5]);
2292 wb_data[1] = ((params->mac_addr[0] << 8) |
2293 params->mac_addr[1]);
2311 bnx2x_update_pfc_bmac1(params, vars);
2332 static int bnx2x_bmac2_enable(struct link_params *params,
2336 struct bnx2x *bp = params->bp;
2337 u8 port = params->port;
2358 wb_data[0] = ((params->mac_addr[2] << 24) |
2359 (params->mac_addr[3] << 16) |
2360 (params->mac_addr[4] << 8) |
2361 params->mac_addr[5]);
2362 wb_data[1] = ((params->mac_addr[0] << 8) |
2363 params->mac_addr[1]);
2392 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2397 static int bnx2x_bmac_enable(struct link_params *params,
2402 u8 port = params->port;
2403 struct bnx2x *bp = params->bp;
2420 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2422 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2427 if ((params->feature_config_flags &
2468 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2471 struct bnx2x *bp = params->bp;
2472 u8 port = params->port;
2816 static u8 bnx2x_eee_has_cap(struct link_params *params)
2818 struct bnx2x *bp = params->bp;
2820 if (REG_RD(bp, params->shmem2_base) <=
2821 offsetof(struct shmem2_region, eee_status[params->port]))
2867 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2870 struct bnx2x *bp = params->bp;
2872 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2873 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2875 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2878 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2885 eee_mode = ((REG_RD(bp, params->shmem_base +
2887 port_feature_config[params->port].
2899 static int bnx2x_eee_set_timers(struct link_params *params,
2903 struct bnx2x *bp = params->bp;
2905 eee_idle = bnx2x_eee_calc_timer(params);
2908 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2910 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2911 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2912 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2918 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2932 static int bnx2x_eee_initial_config(struct link_params *params,
2937 /* Propagate params' bits --> vars (for migration exposure) */
2938 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2943 if (params->eee_mode & EEE_MODE_ADV_LPI)
2948 return bnx2x_eee_set_timers(params, vars);
2952 struct link_params *params,
2955 struct bnx2x *bp = params->bp;
2958 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2968 struct link_params *params,
2971 struct bnx2x *bp = params->bp;
2975 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2994 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2996 struct bnx2x *bp = params->bp;
2998 if (bnx2x_eee_has_cap(params))
2999 REG_WR(bp, params->shmem2_base +
3001 eee_status[params->port]), eee_status);
3005 struct link_params *params,
3008 struct bnx2x *bp = params->bp;
3054 static void bnx2x_bsc_module_sel(struct link_params *params)
3059 struct bnx2x *bp = params->bp;
3060 u8 port = params->port;
3062 board_cfg = REG_RD(bp, params->shmem_base +
3070 sfp_ctrl = REG_RD(bp, params->shmem_base +
3080 static int bnx2x_bsc_read(struct link_params *params,
3097 bnx2x_bsc_module_sel(params);
3188 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3195 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3196 if (params->phy[phy_index].addr == phy_addr) {
3197 return bnx2x_cl45_read(params->bp,
3198 ¶ms->phy[phy_index], devad,
3205 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3212 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3213 if (params->phy[phy_index].addr == phy_addr) {
3214 return bnx2x_cl45_write(params->bp,
3215 ¶ms->phy[phy_index], devad,
3222 struct link_params *params)
3225 struct bnx2x *bp = params->bp;
3230 port = params->port;
3275 static void bnx2x_set_aer_mmd(struct link_params *params,
3280 struct bnx2x *bp = params->bp;
3281 ser_lane = ((params->lane_config &
3289 aer_val = bnx2x_get_warpcore_lane(phy, params);
3346 struct link_params *params,
3349 struct bnx2x *bp = params->bp;
3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3360 static void bnx2x_xgxs_deassert(struct link_params *params)
3362 struct bnx2x *bp = params->bp;
3366 port = params->port;
3374 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params,
3379 struct link_params *params, u16 *ieee_fc)
3381 struct bnx2x *bp = params->bp;
3389 switch (params->req_fc_auto_adv) {
3419 static void set_phy_vars(struct link_params *params,
3422 struct bnx2x *bp = params->bp;
3424 u8 phy_config_swapped = params->multi_phy_config &
3426 for (phy_index = INT_PHY; phy_index < params->num_phys;
3436 params->phy[actual_phy_idx].req_flow_ctrl =
3437 params->req_flow_ctrl[link_cfg_idx];
3439 params->phy[actual_phy_idx].req_line_speed =
3440 params->req_line_speed[link_cfg_idx];
3442 params->phy[actual_phy_idx].speed_cap_mask =
3443 params->speed_cap_mask[link_cfg_idx];
3445 params->phy[actual_phy_idx].req_duplex =
3446 params->req_duplex[link_cfg_idx];
3448 if (params->req_line_speed[link_cfg_idx] ==
3454 params->phy[actual_phy_idx].req_flow_ctrl,
3455 params->phy[actual_phy_idx].req_line_speed,
3456 params->phy[actual_phy_idx].speed_cap_mask);
3460 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3465 struct bnx2x *bp = params->bp;
3472 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3488 struct link_params *params,
3492 struct bnx2x *bp = params->bp;
3513 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
3535 struct link_params *params,
3541 struct bnx2x *bp = params->bp;
3546 SINGLE_MEDIA_DIRECT(params)) {
3547 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3585 bnx2x_pause_resolve(phy, params, vars, pause_result);
3590 struct link_params *params,
3598 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3602 vars->flow_ctrl = params->req_fc_auto_adv;
3605 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3629 struct link_params *params,
3632 struct bnx2x *bp = params->bp;
3663 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3664 bnx2x_update_link_attr(params, params->link_attr_sync);
3667 static void bnx2x_disable_kr2(struct link_params *params,
3671 struct bnx2x *bp = params->bp;
3696 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3697 bnx2x_update_link_attr(params, params->link_attr_sync);
3703 struct link_params *params)
3705 struct bnx2x *bp = params->bp;
3715 struct link_params *params)
3718 struct bnx2x *bp = params->bp;
3719 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3726 bnx2x_set_aer_mmd(params, phy);
3730 struct link_params *params,
3734 struct bnx2x *bp = params->bp;
3780 bnx2x_set_aer_mmd(params, phy);
3785 lane = bnx2x_get_warpcore_lane(phy, params);
3812 if (REG_RD(bp, params->shmem_base +
3814 port_hw_config[params->port].default_cfg)) &
3823 bnx2x_ext_phy_set_pause(params, phy, vars);
3845 bnx2x_set_aer_mmd(params, phy);
3847 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3852 wc_lane_config = REG_RD(bp, params->shmem_base +
3874 bnx2x_disable_kr2(params, vars, phy);
3878 bnx2x_warpcore_restart_AN_KR(phy, params);
3882 struct link_params *params,
3885 struct bnx2x *bp = params->bp;
3904 lane = bnx2x_get_warpcore_lane(phy, params);
3921 bnx2x_set_aer_mmd(params, phy);
3950 struct link_params *params,
3953 struct bnx2x *bp = params->bp;
4004 cfg_tap_val = REG_RD(bp, params->shmem_base +
4006 port_hw_config[params->port].
4054 lane = bnx2x_get_warpcore_lane(phy, params);
4070 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4086 struct link_params *params)
4089 struct bnx2x *bp = params->bp;
4098 bnx2x_set_aer_mmd(params, phy);
4135 bnx2x_set_aer_mmd(params, phy);
4193 struct link_params *params,
4197 struct bnx2x *bp = params->bp;
4204 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4293 struct link_params *params,
4296 struct bnx2x *bp = params->bp;
4322 lane = bnx2x_get_warpcore_lane(phy, params);
4368 struct link_params *params)
4370 struct bnx2x *bp = params->bp;
4373 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4374 params->shmem_base, params->port,
4386 struct link_params *params)
4389 struct bnx2x *bp = params->bp;
4391 lane = bnx2x_get_warpcore_lane(phy, params);
4400 struct link_params *params,
4403 struct bnx2x *bp = params->bp;
4413 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4414 serdes_net_if = (REG_RD(bp, params->shmem_base +
4416 port_hw_config[params->port].default_cfg)) &
4449 } /*params->rx_tx_asic_rst*/
4453 struct link_params *params)
4455 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4456 struct bnx2x *bp = params->bp;
4457 bnx2x_warpcore_clear_regs(phy, params, lane);
4458 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4462 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4465 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4469 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4473 struct bnx2x *bp = params->bp;
4475 u8 port = params->port;
4477 cfg_pin = REG_RD(bp, params->shmem_base +
4491 struct link_params *params,
4494 struct bnx2x *bp = params->bp;
4497 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4498 serdes_net_if = (REG_RD(bp, params->shmem_base +
4500 port_hw_config[params->port].default_cfg)) &
4505 bnx2x_set_aer_mmd(params, phy);
4514 bnx2x_warpcore_clear_regs(phy, params, lane);
4515 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4520 if (params->loopback_mode != LOOPBACK_EXT)
4521 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4524 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4529 bnx2x_warpcore_clear_regs(phy, params, lane);
4532 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4534 if (SINGLE_MEDIA_DIRECT(params)) {
4542 params,
4554 if ((params->loopback_mode == LOOPBACK_NONE) ||
4555 (params->loopback_mode == LOOPBACK_EXT)) {
4556 if (bnx2x_is_sfp_module_plugged(phy, params))
4557 bnx2x_sfp_module_detection(phy, params);
4559 bnx2x_sfp_e3_set_transmitter(params,
4563 bnx2x_warpcore_config_sfi(phy, params);
4575 bnx2x_sfp_module_detection(phy, params);
4578 if (!params->loopback_mode) {
4579 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4582 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4599 struct link_params *params)
4601 struct bnx2x *bp = params->bp;
4603 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4604 bnx2x_set_mdio_emac_per_phy(bp, params);
4605 bnx2x_set_aer_mmd(params, phy);
4627 lane = bnx2x_get_warpcore_lane(phy, params);
4649 bnx2x_set_aer_mmd(params, phy);
4654 struct link_params *params)
4656 struct bnx2x *bp = params->bp;
4660 params->loopback_mode, phy->req_line_speed);
4674 lane = bnx2x_get_warpcore_lane(phy, params);
4685 bnx2x_set_aer_mmd(params, phy);
4698 static void bnx2x_sync_link(struct link_params *params,
4701 struct bnx2x *bp = params->bp;
4804 void bnx2x_link_status_update(struct link_params *params,
4807 struct bnx2x *bp = params->bp;
4808 u8 port = params->port;
4811 set_phy_vars(params, vars);
4813 vars->link_status = REG_RD(bp, params->shmem_base +
4818 if (params->loopback_mode != LOOPBACK_NONE &&
4819 params->loopback_mode != LOOPBACK_EXT)
4822 if (bnx2x_eee_has_cap(params))
4823 vars->eee_status = REG_RD(bp, params->shmem2_base +
4825 eee_status[params->port]));
4828 bnx2x_sync_link(params, vars);
4830 sync_offset = params->shmem_base +
4835 params->phy[INT_PHY].media_type =
4838 params->phy[EXT_PHY1].media_type =
4841 params->phy[EXT_PHY2].media_type =
4847 sync_offset = params->shmem_base +
4855 params->feature_config_flags |=
4858 params->feature_config_flags &=
4862 params->link_attr_sync = SHMEM2_RD(bp,
4863 link_attr_sync[params->port]);
4871 static void bnx2x_set_master_ln(struct link_params *params,
4874 struct bnx2x *bp = params->bp;
4876 ser_lane = ((params->lane_config &
4892 static int bnx2x_reset_unicore(struct link_params *params,
4896 struct bnx2x *bp = params->bp;
4910 bnx2x_set_serdes_access(bp, params->port);
4930 params->port);
4936 static void bnx2x_set_swap_lanes(struct link_params *params,
4939 struct bnx2x *bp = params->bp;
4945 rx_lane_swap = ((params->lane_config &
4948 tx_lane_swap = ((params->lane_config &
4979 struct link_params *params)
4981 struct bnx2x *bp = params->bp;
5032 struct link_params *params,
5036 struct bnx2x *bp = params->bp;
5136 struct link_params *params,
5139 struct bnx2x *bp = params->bp;
5185 struct link_params *params)
5187 struct bnx2x *bp = params->bp;
5205 struct link_params *params,
5208 struct bnx2x *bp = params->bp;
5226 struct link_params *params,
5229 struct bnx2x *bp = params->bp;
5266 struct link_params *params,
5269 struct bnx2x *bp = params->bp;
5331 bnx2x_restart_autoneg(phy, params, 0);
5338 struct link_params *params)
5340 struct bnx2x *bp = params->bp;
5354 params->port);
5365 params->port);
5372 struct link_params *params,
5379 struct bnx2x *bp = params->bp;
5414 bnx2x_pause_resolve(phy, params, vars, pause_result);
5419 struct link_params *params,
5423 struct bnx2x *bp = params->bp;
5430 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5434 vars->flow_ctrl = params->req_fc_auto_adv;
5437 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5438 vars->flow_ctrl = params->req_fc_auto_adv;
5441 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5447 struct link_params *params)
5449 struct bnx2x *bp = params->bp;
5510 bnx2x_restart_autoneg(phy, params, 0);
5515 struct link_params *params,
5523 if (bnx2x_direct_parallel_detect_used(phy, params))
5528 struct link_params *params,
5534 struct bnx2x *bp = params->bp;
5619 struct link_params *params,
5622 struct bnx2x *bp = params->bp;
5639 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5645 if (SINGLE_MEDIA_DIRECT(params)) {
5647 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5649 bnx2x_xgxs_an_resolve(phy, params, vars,
5654 SINGLE_MEDIA_DIRECT(params)) {
5656 bnx2x_check_fallback_to_cl37(phy, params);
5661 if (SINGLE_MEDIA_DIRECT(params) &&
5693 struct link_params *params,
5696 struct bnx2x *bp = params->bp;
5700 lane = bnx2x_get_warpcore_lane(phy, params);
5702 if ((params->loopback_mode) &&
5720 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5739 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5758 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5764 SINGLE_MEDIA_DIRECT(params)) {
5805 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5817 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5819 struct bnx2x *bp = params->bp;
5820 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5856 static int bnx2x_emac_program(struct link_params *params,
5859 struct bnx2x *bp = params->bp;
5860 u8 port = params->port;
5899 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5904 struct link_params *params)
5908 struct bnx2x *bp = params->bp;
5928 struct link_params *params,
5931 struct bnx2x *bp = params->bp;
5932 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5933 (params->loopback_mode == LOOPBACK_XGXS));
5935 if (SINGLE_MEDIA_DIRECT(params) &&
5936 (params->feature_config_flags &
5938 bnx2x_set_preemphasis(phy, params);
5942 (SINGLE_MEDIA_DIRECT(params) &&
5943 params->loopback_mode == LOOPBACK_EXT)) {
5947 bnx2x_set_autoneg(phy, params, vars, 0);
5950 bnx2x_program_serdes(phy, params, vars);
5956 bnx2x_set_brcm_cl37_advertisement(phy, params);
5959 bnx2x_set_ieee_aneg_advertisement(phy, params,
5963 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5966 bnx2x_restart_autoneg(phy, params, enable_cl73);
5972 bnx2x_initialize_sgmii_process(phy, params, vars);
5977 struct link_params *params,
5995 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5996 bnx2x_set_aer_mmd(params, phy);
5998 bnx2x_set_master_ln(params, phy);
6000 rc = bnx2x_reset_unicore(params, phy, 0);
6005 bnx2x_set_aer_mmd(params, phy);
6008 bnx2x_set_master_ln(params, phy);
6009 bnx2x_set_swap_lanes(params, phy);
6017 struct link_params *params)
6037 params->port);
6042 static void bnx2x_link_int_enable(struct link_params *params)
6044 u8 port = params->port;
6046 struct bnx2x *bp = params->bp;
6051 if (!(SINGLE_MEDIA_DIRECT(params)))
6053 } else if (params->switch_cfg == SWITCH_CFG_10G) {
6057 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6058 params->phy[INT_PHY].type !=
6067 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6068 params->phy[INT_PHY].type !=
6079 (params->switch_cfg == SWITCH_CFG_10G),
6124 static void bnx2x_link_int_ack(struct link_params *params,
6127 struct bnx2x *bp = params->bp;
6128 u8 port = params->port;
6143 else if (params->switch_cfg == SWITCH_CFG_10G) {
6148 ((params->lane_config &
6203 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6211 if (version == NULL || params == NULL || len == 0)
6213 bp = params->bp;
6217 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6219 if (params->phy[EXT_PHY1].format_fw_ver) {
6220 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6225 if ((params->num_phys == MAX_PHYS) &&
6226 (params->phy[EXT_PHY2].ver_addr != 0)) {
6227 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6228 if (params->phy[EXT_PHY2].format_fw_ver) {
6232 status |= params->phy[EXT_PHY2].format_fw_ver(
6244 struct link_params *params)
6246 u8 port = params->port;
6247 struct bnx2x *bp = params->bp;
6276 bnx2x_set_aer_mmd(params, phy);
6298 int bnx2x_set_led(struct link_params *params,
6301 u8 port = params->port;
6302 u16 hw_led_mode = params->hw_led_mode;
6307 struct bnx2x *bp = params->bp;
6313 if (params->phy[phy_idx].set_link_led) {
6314 params->phy[phy_idx].set_link_led(
6315 ¶ms->phy[phy_idx], params, mode);
6327 if (params->phy[EXT_PHY1].type ==
6346 if (((params->phy[EXT_PHY1].type ==
6348 (params->phy[EXT_PHY1].type ==
6350 CHIP_IS_E2(bp) && params->num_phys == 2) {
6368 } else if (SINGLE_MEDIA_DIRECT(params)) {
6384 } else if ((params->phy[EXT_PHY1].type ==
6396 u32 nig_led_mode = ((params->hw_led_mode <<
6447 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6450 struct bnx2x *bp = params->bp;
6454 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6458 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6468 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6488 if (params->loopback_mode == LOOPBACK_XGXS)
6491 switch (params->num_phys) {
6496 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6497 ¶ms->phy[EXT_PHY1],
6498 params, &temp_vars);
6501 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6503 serdes_phy_type = ((params->phy[phy_index].media_type ==
6505 (params->phy[phy_index].media_type ==
6507 (params->phy[phy_index].media_type ==
6509 (params->phy[phy_index].media_type ==
6514 if (params->phy[phy_index].read_status) {
6516 params->phy[phy_index].read_status(
6517 ¶ms->phy[phy_index],
6518 params, &temp_vars);
6528 static int bnx2x_link_initialize(struct link_params *params,
6532 struct bnx2x *bp = params->bp;
6538 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6545 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6547 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6548 (params->loopback_mode == LOOPBACK_XGXS));
6551 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6552 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6553 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6557 bnx2x_set_parallel_detection(phy, params);
6558 if (params->phy[INT_PHY].config_init)
6559 params->phy[INT_PHY].config_init(phy, params, vars);
6565 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6569 if (params->phy[INT_PHY].supported &
6573 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6580 if (params->phy[phy_index].supported &
6585 (bnx2x_phy_selection(params) ==
6591 params->phy[phy_index].config_init(
6592 ¶ms->phy[phy_index],
6593 params, vars);
6598 params->port*4,
6607 struct link_params *params)
6610 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6611 (0x1ff << (params->port*16)));
6615 struct link_params *params)
6617 struct bnx2x *bp = params->bp;
6623 gpio_port = params->port;
6633 static int bnx2x_update_link_down(struct link_params *params,
6636 struct bnx2x *bp = params->bp;
6637 u8 port = params->port;
6640 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6648 bnx2x_update_mng(params, vars->link_status);
6661 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6665 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6667 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6672 bnx2x_update_mng_eee(params, vars->eee_status);
6673 bnx2x_set_xmac_rxtx(params, 0);
6674 bnx2x_set_umac_rxtx(params, 0);
6680 static int bnx2x_update_link_up(struct link_params *params,
6684 struct bnx2x *bp = params->bp;
6685 u8 phy_idx, port = params->port;
6701 if (bnx2x_xmac_enable(params, vars, 0) ==
6709 bnx2x_umac_enable(params, vars, 0);
6710 bnx2x_set_led(params, vars,
6717 (params->port << 2), 1);
6720 (params->port << 2), 0xfc20);
6726 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6734 bnx2x_set_led(params, vars,
6737 rc = bnx2x_emac_program(params, vars);
6738 bnx2x_emac_enable(params, vars, 0);
6744 SINGLE_MEDIA_DIRECT(params))
6745 bnx2x_set_gmii_tx_driver(params);
6751 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6758 bnx2x_update_mng(params, vars->link_status);
6759 bnx2x_update_mng_eee(params, vars->eee_status);
6762 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6763 bnx2x_check_half_open_conn(params, vars, 0);
6771 static void bnx2x_chng_link_count(struct link_params *params, bool clear)
6773 struct bnx2x *bp = params->bp;
6780 addr = params->shmem2_base +
6781 offsetof(struct shmem2_region, link_change_count[params->port]);
6801 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6803 struct bnx2x *bp = params->bp;
6805 u8 port = params->port;
6815 for (phy_index = INT_PHY; phy_index < params->num_phys;
6829 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6857 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6859 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6862 /* Read link status and params of this ext phy */
6863 cur_link_up = phy->read_status(phy, params,
6878 switch (bnx2x_phy_selection(params)) {
6905 params->multi_phy_config);
6918 if (params->phy[INT_PHY].read_status)
6919 params->phy[INT_PHY].read_status(
6920 ¶ms->phy[INT_PHY],
6921 params, vars);
6940 if (params->phy[EXT_PHY2].phy_specific_func) {
6943 params->phy[EXT_PHY2].phy_specific_func(
6944 ¶ms->phy[EXT_PHY2],
6945 params, DISABLE_TX);
6951 if (params->phy[active_external_phy].supported &
6963 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6965 if (params->phy[phy_index].flags &
6982 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6990 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6999 bnx2x_link_int_ack(params, vars, link_10g_plus);
7008 if (!(SINGLE_MEDIA_DIRECT(params))) {
7012 params->phy[EXT_PHY1].flags &
7014 if (!(params->phy[EXT_PHY1].flags &
7023 if (params->phy[INT_PHY].config_init)
7024 params->phy[INT_PHY].config_init(
7025 ¶ms->phy[INT_PHY], params,
7034 SINGLE_MEDIA_DIRECT(params)) &&
7038 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7044 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7046 rc = bnx2x_update_link_down(params, vars);
7049 bnx2x_chng_link_count(params, false);
7052 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7115 struct link_params *params,
7118 struct bnx2x *bp = params->bp;
7125 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7142 bnx2x_pause_resolve(phy, params, vars, pause_result);
7323 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7328 struct bnx2x *bp = params->bp;
7334 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7359 struct link_params *params,
7362 struct bnx2x *bp = params->bp;
7375 struct link_params *params,
7378 struct bnx2x *bp = params->bp;
7386 gpio_port = params->port;
7394 bnx2x_8073_specific_func(phy, params, PHY_INIT);
7395 bnx2x_8073_set_pause_cl37(params, phy, vars);
7406 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7421 if (REG_RD(bp, params->shmem_base +
7423 port_hw_config[params->port].default_cfg)) &
7434 if (params->loopback_mode == LOOPBACK_EXT) {
7512 bnx2x_ext_phy_set_pause(params, phy, vars);
7522 struct link_params *params,
7525 struct bnx2x *bp = params->bp;
7606 params->port);
7611 params->port);
7616 params->port);
7620 params->port);
7625 if (params->lane_config &
7647 bnx2x_8073_resolve_fc(phy, params, vars);
7667 struct link_params *params)
7669 struct bnx2x *bp = params->bp;
7674 gpio_port = params->port;
7686 struct link_params *params,
7689 struct bnx2x *bp = params->bp;
7693 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7695 bnx2x_ext_phy_hw_reset(bp, params->port);
7697 bnx2x_wait_reset_complete(bp, phy, params);
7708 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7712 struct link_params *params,
7717 struct bnx2x *bp = params->bp;
7739 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7747 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7751 struct bnx2x *bp = params->bp;
7756 if (params->feature_config_flags &
7770 static u8 bnx2x_get_gpio_port(struct link_params *params)
7774 struct bnx2x *bp = params->bp;
7778 gpio_port = params->port;
7784 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7789 u8 port = params->port;
7790 struct bnx2x *bp = params->bp;
7794 tx_en_mode = REG_RD(bp, params->shmem_base +
7831 gpio_port = bnx2x_get_gpio_port(params);
7841 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7845 struct bnx2x *bp = params->bp;
7848 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7850 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7854 struct link_params *params,
7858 struct bnx2x *bp = params->bp;
7920 static void bnx2x_warpcore_power_module(struct link_params *params,
7924 struct bnx2x *bp = params->bp;
7926 pin_cfg = (REG_RD(bp, params->shmem_base +
7928 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7942 struct link_params *params,
7951 struct bnx2x *bp = params->bp;
7963 bnx2x_warpcore_power_module(params, 0);
7966 bnx2x_warpcore_power_module(params, 1);
7968 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7983 struct link_params *params,
7987 struct bnx2x *bp = params->bp;
8078 struct link_params *params, u8 dev_addr,
8082 struct bnx2x *bp = params->bp;
8110 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8120 struct link_params *params,
8123 struct bnx2x *bp = params->bp;
8130 params,
8138 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8139 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8141 bnx2x_update_link_attr(params, params->link_attr_sync);
8188 u8 gport = params->port;
8192 (params->port << 1);
8200 bnx2x_sfp_set_transmitter(params, phy, 0);
8202 bnx2x_sfp_set_transmitter(params, phy, 1);
8208 if (params->phy[idx].type == phy->type) {
8214 phy->req_line_speed = params->req_line_speed[cfg_idx];
8222 sync_offset = params->shmem_base +
8224 dev_info.port_hw_config[params->port].media_type);
8228 if (&(params->phy[phy_idx]) == phy) {
8241 params,
8262 struct link_params *params)
8264 struct bnx2x *bp = params->bp;
8270 val = REG_RD(bp, params->shmem_base +
8272 port_feature_config[params->port].config));
8279 if (params->feature_config_flags &
8283 } else if (params->feature_config_flags &
8286 if (DUAL_MEDIA(params)) {
8308 params,
8317 params,
8328 params->port, vendor_name, vendor_pn);
8336 struct link_params *params)
8341 struct bnx2x *bp = params->bp;
8350 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8353 rc = bnx2x_read_sfp_module_eeprom(phy, params,
8364 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8485 struct link_params *params,
8488 struct bnx2x *bp = params->bp;
8492 bnx2x_sfp_set_transmitter(params, phy, 0);
8496 bnx2x_sfp_set_transmitter(params, phy, 1);
8530 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8533 struct bnx2x *bp = params->bp;
8535 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8537 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8547 u8 gpio_port = bnx2x_get_gpio_port(params);
8562 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8566 u8 port = params->port;
8567 struct bnx2x *bp = params->bp;
8568 pin_cfg = (REG_RD(bp, params->shmem_base +
8578 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8581 struct bnx2x *bp = params->bp;
8587 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8589 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8593 struct link_params *params)
8595 struct bnx2x *bp = params->bp;
8596 bnx2x_warpcore_power_module(params, 0);
8606 static void bnx2x_power_sfp_module(struct link_params *params,
8610 struct bnx2x *bp = params->bp;
8616 bnx2x_8727_power_module(params->bp, phy, power);
8619 bnx2x_warpcore_power_module(params, power);
8625 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8631 struct bnx2x *bp = params->bp;
8633 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8665 static void bnx2x_set_limiting_mode(struct link_params *params,
8671 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8675 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8678 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8684 struct link_params *params)
8686 struct bnx2x *bp = params->bp;
8690 u32 val = REG_RD(bp, params->shmem_base +
8692 port_feature_config[params->port].config));
8694 bnx2x_sfp_set_transmitter(params, phy, 1);
8696 params->port);
8698 bnx2x_power_sfp_module(params, phy, 1);
8699 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8702 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8707 bnx2x_set_sfp_module_fault_led(params,
8714 bnx2x_power_sfp_module(params, phy, 0);
8719 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8725 bnx2x_set_limiting_mode(params, phy, edc_mode);
8733 bnx2x_sfp_set_transmitter(params, phy, 0);
8738 void bnx2x_handle_module_detect_int(struct link_params *params)
8740 struct bnx2x *bp = params->bp;
8745 phy = ¶ms->phy[INT_PHY];
8747 bnx2x_sfp_set_transmitter(params, phy, 1);
8749 phy = ¶ms->phy[EXT_PHY1];
8751 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8752 params->port, &gpio_num, &gpio_port) ==
8759 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8766 bnx2x_set_mdio_emac_per_phy(bp, params);
8767 bnx2x_set_aer_mmd(params, phy);
8769 bnx2x_power_sfp_module(params, phy, 1);
8773 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8774 bnx2x_sfp_module_detection(phy, params);
8786 (params->link_flags &
8789 bnx2x_warpcore_config_sfi(phy, params);
8834 struct link_params *params,
8839 struct bnx2x *bp = params->bp;
8875 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8896 struct link_params *params,
8901 struct bnx2x *bp = params->bp;
8904 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8906 bnx2x_ext_phy_hw_reset(bp, params->port);
8908 bnx2x_wait_reset_complete(bp, phy, params);
8919 if ((params->feature_config_flags &
8978 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8984 tx_en_mode = REG_RD(bp, params->shmem_base +
8986 dev_info.port_hw_config[params->port].sfp_ctrl))
9000 struct link_params *params,
9003 return bnx2x_8706_8726_read_status(phy, params, vars);
9010 struct link_params *params)
9012 struct bnx2x *bp = params->bp;
9018 struct link_params *params)
9020 struct bnx2x *bp = params->bp;
9052 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9056 struct link_params *params,
9059 struct bnx2x *bp = params->bp;
9061 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9077 struct link_params *params,
9080 struct bnx2x *bp = params->bp;
9084 bnx2x_wait_reset_complete(bp, phy, params);
9086 bnx2x_8726_external_rom_boot(phy, params);
9093 bnx2x_sfp_module_detection(phy, params);
9114 bnx2x_ext_phy_set_pause(params, phy, vars);
9140 if ((params->feature_config_flags &
9159 struct link_params *params)
9161 struct bnx2x *bp = params->bp;
9162 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9174 struct link_params *params, u8 mode)
9176 struct bnx2x *bp = params->bp;
9220 struct link_params *params) {
9226 struct bnx2x *bp = params->bp;
9235 struct link_params *params)
9237 struct bnx2x *bp = params->bp;
9253 if (DUAL_MEDIA(params)) {
9292 struct link_params *params,
9297 struct bnx2x *bp = params->bp;
9300 bnx2x_wait_reset_complete(bp, phy, params);
9304 bnx2x_8727_specific_func(phy, params, PHY_INIT);
9321 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9331 bnx2x_8727_config_speed(phy, params);
9335 if ((params->feature_config_flags &
9352 tx_en_mode = REG_RD(bp, params->shmem_base +
9354 dev_info.port_hw_config[params->port].sfp_ctrl))
9376 struct link_params *params)
9378 struct bnx2x *bp = params->bp;
9380 u32 val = REG_RD(bp, params->shmem_base +
9382 port_feature_config[params->port].
9444 bnx2x_sfp_set_transmitter(params, phy, 0);
9446 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9447 bnx2x_sfp_module_detection(phy, params);
9452 bnx2x_8727_config_speed(phy, params);
9461 struct link_params *params,
9465 struct bnx2x *bp = params->bp;
9466 u8 link_up = 0, oc_port = params->port;
9507 oc_port = BP_PATH(bp) + (params->port << 1);
9536 bnx2x_8727_power_module(params->bp, phy, 0);
9543 bnx2x_8727_handle_mod_abs(phy, params);
9552 bnx2x_sfp_set_transmitter(params, phy, 1);
9569 params->port);
9574 params->port);
9578 params->port);
9595 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9600 if ((DUAL_MEDIA(params)) &&
9620 struct link_params *params)
9622 struct bnx2x *bp = params->bp;
9625 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9628 bnx2x_sfp_set_transmitter(params, phy, 0);
9779 struct link_params *params,
9782 struct bnx2x *bp = params->bp;
9787 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9793 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9802 struct link_params *params,
9805 struct bnx2x *bp = params->bp;
9808 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9817 bnx2x_ext_phy_set_pause(params, phy, vars);
9948 struct link_params *params,
9951 struct bnx2x *bp = params->bp;
9954 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9957 bnx2x_ext_phy_hw_reset(bp, params->port);
9958 bnx2x_wait_reset_complete(bp, phy, params);
9961 bnx2x_848xx_cmn_config_init(phy, params, vars);
9968 struct link_params *params,
9974 struct bnx2x *bp = params->bp;
10045 struct link_params *params, u16 fw_cmd,
10050 struct bnx2x *bp = params->bp;
10123 struct link_params *params,
10128 struct bnx2x *bp = params->bp;
10131 (REG_RD(bp, params->shmem2_base +
10133 link_attr_sync[params->port])) &
10135 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10138 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10144 struct link_params *params,
10150 struct bnx2x *bp = params->bp;
10153 pair_swap = REG_RD(bp, params->shmem_base +
10155 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10164 status = bnx2x_848xx_cmd_hdlr(phy, params,
10212 struct link_params *params)
10214 struct bnx2x *bp = params->bp;
10216 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10230 shmem_base_path[0] = params->shmem_base;
10234 params->chip_id);
10243 struct link_params *params,
10247 struct bnx2x *bp = params->bp;
10253 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10260 return bnx2x_eee_disable(phy, params, vars);
10264 struct link_params *params,
10268 struct bnx2x *bp = params->bp;
10271 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10278 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10283 struct link_params *params,
10286 struct bnx2x *bp = params->bp;
10298 port = params->port;
10311 bnx2x_wait_reset_complete(bp, phy, params);
10322 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
10323 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
10333 params->link_attr_sync |= LINK_ATTR_84858;
10334 bnx2x_update_link_attr(params, params->link_attr_sync);
10355 actual_phy_selection = bnx2x_phy_selection(params);
10375 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10381 params->multi_phy_config, val);
10384 bnx2x_848xx_pair_swap_cfg(phy, params, vars);
10391 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10398 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10400 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10403 u32 cms_enable = REG_RD(bp, params->shmem_base +
10405 dev_info.port_hw_config[params->port].default_cfg)) &
10424 bnx2x_eee_has_cap(params)) {
10425 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10428 bnx2x_8483x_disable_eee(phy, params, vars);
10433 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10434 (bnx2x_eee_calc_timer(params) ||
10435 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10436 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10438 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10483 struct link_params *params,
10486 struct bnx2x *bp = params->bp;
10565 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10605 bnx2x_eee_an_resolve(phy, params, vars);
10629 struct link_params *params)
10631 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10633 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10638 struct link_params *params)
10640 bnx2x_cl45_write(params->bp, phy,
10642 bnx2x_cl45_write(params->bp, phy,
10647 struct link_params *params)
10649 struct bnx2x *bp = params->bp;
10656 port = params->port;
10674 struct link_params *params, u8 mode)
10676 struct bnx2x *bp = params->bp;
10683 port = params->port;
10690 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10741 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10776 params->port*4) &
10778 params->link_flags |=
10784 params->port*4,
10811 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10857 params->port*4) &
10859 params->link_flags |=
10865 params->port*4,
10899 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10944 val = ((params->hw_led_mode <<
10984 if (params->link_flags &
10986 bnx2x_link_int_enable(params);
10987 params->link_flags &=
11008 struct link_params *params,
11011 struct bnx2x *bp = params->bp;
11037 struct link_params *params,
11040 struct bnx2x *bp = params->bp;
11051 port = params->port;
11053 cfg_pin = (REG_RD(bp, params->shmem_base +
11068 bnx2x_wait_reset_complete(bp, phy, params);
11074 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
11089 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11181 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
11191 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11194 bnx2x_eee_disable(phy, params, vars);
11195 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
11197 (bnx2x_eee_calc_timer(params) ||
11198 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
11204 bnx2x_eee_advertise(phy, params, vars,
11208 bnx2x_eee_disable(phy, params, vars);
11216 if (params->feature_config_flags &
11242 struct link_params *params, u8 mode)
11244 struct bnx2x *bp = params->bp;
11278 struct link_params *params)
11280 struct bnx2x *bp = params->bp;
11291 port = params->port;
11292 cfg_pin = (REG_RD(bp, params->shmem_base +
11303 struct link_params *params,
11306 struct bnx2x *bp = params->bp;
11371 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11402 bnx2x_eee_has_cap(params))
11403 bnx2x_eee_an_resolve(phy, params, vars);
11410 struct link_params *params)
11412 struct bnx2x *bp = params->bp;
11414 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11441 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11453 struct link_params *params)
11455 struct bnx2x *bp = params->bp;
11462 struct link_params *params,
11466 struct bnx2x *bp = params->bp;
11471 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11473 bnx2x_ext_phy_hw_reset(bp, params->port);
11474 bnx2x_wait_reset_complete(bp, phy, params);
11482 bnx2x_ext_phy_set_pause(params, phy, vars);
11496 bnx2x_save_spirom_version(bp, params->port,
11501 struct link_params *params,
11504 struct bnx2x *bp = params->bp;
11530 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11579 struct link_params *params) {
11581 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11582 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11584 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11585 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11589 struct link_params *params, u8 mode)
11592 struct bnx2x *bp = params->bp;
12481 static void bnx2x_phy_def_cfg(struct link_params *params,
12485 struct bnx2x *bp = params->bp;
12489 link_config = REG_RD(bp, params->shmem_base +
12491 port_feature_config[params->port].link_config2));
12492 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12495 port_hw_config[params->port].speed_capability_mask2));
12497 link_config = REG_RD(bp, params->shmem_base +
12499 port_feature_config[params->port].link_config));
12500 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12503 port_hw_config[params->port].speed_capability_mask));
12556 u32 bnx2x_phy_selection(struct link_params *params)
12561 phy_config_swapped = params->multi_phy_config &
12564 prio_cfg = params->multi_phy_config &
12588 int bnx2x_phy_probe(struct link_params *params)
12592 struct bnx2x *bp = params->bp;
12594 params->num_phys = 0;
12596 phy_config_swapped = params->multi_phy_config &
12611 phy = ¶ms->phy[actual_phy_idx];
12612 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12613 params->shmem2_base, params->port,
12615 params->num_phys = 0;
12627 if (params->feature_config_flags &
12631 if (!(params->feature_config_flags &
12635 sync_offset = params->shmem_base +
12637 dev_info.port_hw_config[params->port].media_type);
12654 bnx2x_phy_def_cfg(params, phy, phy_index);
12655 params->num_phys++;
12658 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12662 static void bnx2x_init_bmac_loopback(struct link_params *params,
12665 struct bnx2x *bp = params->bp;
12674 bnx2x_xgxs_deassert(params);
12677 bnx2x_bmac_enable(params, vars, 1, 1);
12679 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12682 static void bnx2x_init_emac_loopback(struct link_params *params,
12685 struct bnx2x *bp = params->bp;
12694 bnx2x_xgxs_deassert(params);
12696 bnx2x_emac_enable(params, vars, 1);
12697 bnx2x_emac_program(params, vars);
12698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12701 static void bnx2x_init_xmac_loopback(struct link_params *params,
12704 struct bnx2x *bp = params->bp;
12706 if (!params->req_line_speed[0])
12709 vars->line_speed = params->req_line_speed[0];
12717 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
12718 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
12719 params->phy[INT_PHY].config_loopback(
12720 ¶ms->phy[INT_PHY],
12721 params);
12723 bnx2x_xmac_enable(params, vars, 1);
12724 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12727 static void bnx2x_init_umac_loopback(struct link_params *params,
12730 struct bnx2x *bp = params->bp;
12737 bnx2x_umac_enable(params, vars, 1);
12739 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12742 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12745 struct bnx2x *bp = params->bp;
12746 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
12750 if (params->req_line_speed[0] == SPEED_1000)
12752 else if ((params->req_line_speed[0] == SPEED_20000) ||
12759 bnx2x_xgxs_deassert(params);
12760 bnx2x_link_initialize(params, vars);
12762 if (params->req_line_speed[0] == SPEED_1000) {
12764 bnx2x_umac_enable(params, vars, 0);
12766 bnx2x_emac_program(params, vars);
12767 bnx2x_emac_enable(params, vars, 0);
12771 bnx2x_xmac_enable(params, vars, 0);
12773 bnx2x_bmac_enable(params, vars, 0, 1);
12776 if (params->loopback_mode == LOOPBACK_XGXS) {
12778 int_phy->config_loopback(int_phy, params);
12783 phy_index < params->num_phys; phy_index++)
12784 if (params->phy[phy_index].config_loopback)
12785 params->phy[phy_index].config_loopback(
12786 ¶ms->phy[phy_index],
12787 params);
12789 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12791 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12794 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12796 struct bnx2x *bp = params->bp;
12802 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12805 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12809 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12812 static int bnx2x_avoid_link_flap(struct link_params *params,
12817 struct bnx2x *bp = params->bp;
12819 bnx2x_set_mdio_emac_per_phy(bp, params);
12821 bnx2x_link_status_update(params, vars);
12828 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12829 struct bnx2x_phy *phy = ¶ms->phy[phy_idx];
12832 phy->phy_specific_func(phy, params, PHY_INIT);
12837 bnx2x_verify_sfp_module(phy, params);
12839 lfa_sts = REG_RD(bp, params->lfa_base +
12851 params->port));
12855 params->port));
12858 bnx2x_umac_enable(params, vars, 0);
12860 bnx2x_xmac_enable(params, vars, 0);
12863 bnx2x_emac_enable(params, vars, 0);
12865 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12876 REG_WR(bp, params->lfa_base +
12880 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12883 bnx2x_link_int_enable(params);
12887 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12892 struct bnx2x *bp = params->bp;
12894 bnx2x_link_reset(params, vars, 1);
12896 if (!params->lfa_base)
12899 REG_WR(bp, params->lfa_base +
12901 params->req_duplex[0] | (params->req_duplex[1] << 16));
12903 REG_WR(bp, params->lfa_base +
12905 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12907 REG_WR(bp, params->lfa_base +
12909 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12912 REG_WR(bp, params->lfa_base +
12915 params->speed_cap_mask[cfg_idx]);
12918 tmp_val = REG_RD(bp, params->lfa_base +
12921 tmp_val |= params->req_fc_auto_adv;
12923 REG_WR(bp, params->lfa_base +
12926 lfa_sts = REG_RD(bp, params->lfa_base +
12942 REG_WR(bp, params->lfa_base +
12947 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12950 struct bnx2x *bp = params->bp;
12953 params->req_line_speed[0], params->req_flow_ctrl[0]);
12955 params->req_line_speed[1], params->req_flow_ctrl[1]);
12956 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12966 params->link_flags = PHY_INITIALIZED;
12968 bnx2x_set_rx_filter(params, 1);
12969 bnx2x_chng_link_count(params, true);
12971 lfa_status = bnx2x_check_lfa(params);
12975 return bnx2x_avoid_link_flap(params, vars);
12980 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12983 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12989 bnx2x_emac_init(params, vars);
12991 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12994 if (params->num_phys == 0) {
12998 set_phy_vars(params, vars);
13000 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
13001 switch (params->loopback_mode) {
13003 bnx2x_init_bmac_loopback(params, vars);
13006 bnx2x_init_emac_loopback(params, vars);
13009 bnx2x_init_xmac_loopback(params, vars);
13012 bnx2x_init_umac_loopback(params, vars);
13016 bnx2x_init_xgxs_loopback(params, vars);
13020 if (params->switch_cfg == SWITCH_CFG_10G)
13021 bnx2x_xgxs_deassert(params);
13023 bnx2x_serdes_deassert(bp, params->port);
13025 bnx2x_link_initialize(params, vars);
13027 bnx2x_link_int_enable(params);
13030 bnx2x_update_mng(params, vars->link_status);
13032 bnx2x_update_mng_eee(params, vars->eee_status);
13036 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
13039 struct bnx2x *bp = params->bp;
13040 u8 phy_index, port = params->port, clear_latch_ind = 0;
13044 bnx2x_chng_link_count(params, true);
13045 bnx2x_update_mng(params, vars->link_status);
13048 bnx2x_update_mng_eee(params, vars->eee_status);
13065 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
13067 bnx2x_set_xmac_rxtx(params, 0);
13068 bnx2x_set_umac_rxtx(params, 0);
13079 bnx2x_set_mdio_emac_per_phy(bp, params);
13080 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
13083 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
13085 if (params->phy[phy_index].link_reset) {
13086 bnx2x_set_aer_mmd(params,
13087 ¶ms->phy[phy_index]);
13088 params->phy[phy_index].link_reset(
13089 ¶ms->phy[phy_index],
13090 params);
13092 if (params->phy[phy_index].flags &
13104 if (params->phy[INT_PHY].link_reset)
13105 params->phy[INT_PHY].link_reset(
13106 ¶ms->phy[INT_PHY], params);
13116 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13117 bnx2x_set_xumac_nig(params, 0, 0);
13127 int bnx2x_lfa_reset(struct link_params *params,
13130 struct bnx2x *bp = params->bp;
13133 params->link_flags &= ~PHY_INITIALIZED;
13134 if (!params->lfa_base)
13135 return bnx2x_link_reset(params, vars, 1);
13140 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13147 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
13150 bnx2x_set_xmac_rxtx(params, 0);
13151 bnx2x_set_umac_rxtx(params, 0);
13159 bnx2x_set_rx_filter(params, 0);
13168 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
13171 bnx2x_set_xmac_rxtx(params, 1);
13172 bnx2x_set_umac_rxtx(params, 1);
13175 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13614 static void bnx2x_check_over_curr(struct link_params *params,
13617 struct bnx2x *bp = params->bp;
13619 u8 port = params->port;
13622 cfg_pin = (REG_RD(bp, params->shmem_base +
13641 params->port);
13643 bnx2x_warpcore_power_module(params, 0);
13650 static u8 bnx2x_analyze_link_error(struct link_params *params,
13654 struct bnx2x *bp = params->bp;
13690 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13703 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13705 bnx2x_sync_link(params, vars);
13707 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13710 bnx2x_update_mng(params, vars->link_status);
13729 static int bnx2x_check_half_open_conn(struct link_params *params,
13733 struct bnx2x *bp = params->bp;
13738 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13749 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13759 bnx2x_analyze_link_error(params, vars, lss_status,
13763 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13767 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13778 bnx2x_analyze_link_error(params, vars, lss_status,
13785 struct link_params *params,
13788 struct bnx2x *bp = params->bp;
13790 u8 led_change, port = params->port;
13793 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13803 led_change = bnx2x_analyze_link_error(params, vars, value,
13823 bnx2x_set_e3_module_fault_led(params, led_mode);
13827 static void bnx2x_kr2_recovery(struct link_params *params,
13831 struct bnx2x *bp = params->bp;
13833 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13834 bnx2x_warpcore_restart_AN_KR(phy, params);
13837 static void bnx2x_check_kr2_wa(struct link_params *params,
13841 struct bnx2x *bp = params->bp;
13855 sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13857 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13858 bnx2x_kr2_recovery(params, vars, phy);
13864 lane = bnx2x_get_warpcore_lane(phy, params);
13871 bnx2x_set_aer_mmd(params, phy);
13875 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13876 bnx2x_kr2_recovery(params, vars, phy);
13891 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13895 bnx2x_kr2_recovery(params, vars, phy);
13903 bnx2x_disable_kr2(params, vars, phy);
13905 bnx2x_warpcore_restart_AN_KR(phy, params);
13910 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13913 struct bnx2x *bp = params->bp;
13915 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13916 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13917 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13925 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
13926 bnx2x_set_aer_mmd(params, phy);
13931 bnx2x_check_kr2_wa(params, vars, phy);
13932 bnx2x_check_over_curr(params, vars);
13934 bnx2x_warpcore_config_runtime(phy, params, vars);
13936 if ((REG_RD(bp, params->shmem_base +
13938 port_hw_config[params->port].default_cfg))
13941 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13942 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13949 bnx2x_update_mng(params, vars->link_status);
13976 void bnx2x_hw_reset_phy(struct link_params *params)
13979 struct bnx2x *bp = params->bp;
13980 bnx2x_update_mng(params, 0);
13981 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13989 if (params->phy[phy_index].hw_reset) {
13990 params->phy[phy_index].hw_reset(
13991 ¶ms->phy[phy_index],
13992 params);
13993 params->phy[phy_index] = phy_null;