Lines Matching defs:cfg_pin
4333 u32 cfg_pin;
4337 cfg_pin = (REG_RD(bp, shmem_base +
4349 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4350 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4353 cfg_pin);
4357 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4358 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4474 u32 cfg_pin;
4477 cfg_pin = REG_RD(bp, params->shmem_base +
4485 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4487 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
11043 u32 cfg_pin;
11053 cfg_pin = (REG_RD(bp, params->shmem_base +
11060 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
11281 u32 cfg_pin;
11292 cfg_pin = (REG_RD(bp, params->shmem_base +
11299 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
13618 u32 cfg_pin;
13622 cfg_pin = (REG_RD(bp, params->shmem_base +
13629 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13789 u32 cfg_pin, value = 0;
13793 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13798 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13799 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);