Lines Matching defs:lp
98 static int amd8111e_read_phy(struct amd8111e_priv *lp,
101 void __iomem *mmio = lp->mmio;
127 static int amd8111e_write_phy(struct amd8111e_priv *lp,
131 void __iomem *mmio = lp->mmio;
159 struct amd8111e_priv *lp = netdev_priv(dev);
162 amd8111e_read_phy(lp, phy_id, reg_num, ®_val);
171 struct amd8111e_priv *lp = netdev_priv(dev);
173 amd8111e_write_phy(lp, phy_id, reg_num, val);
181 struct amd8111e_priv *lp = netdev_priv(dev);
185 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
187 switch (lp->ext_phy_option) {
208 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
210 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
212 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
221 struct amd8111e_priv *lp = netdev_priv(dev);
227 if (lp->tx_skbuff[i]) {
228 dma_unmap_single(&lp->pci_dev->dev,
229 lp->tx_dma_addr[i],
230 lp->tx_skbuff[i]->len, DMA_TO_DEVICE);
231 dev_kfree_skb(lp->tx_skbuff[i]);
232 lp->tx_skbuff[i] = NULL;
233 lp->tx_dma_addr[i] = 0;
238 rx_skbuff = lp->rx_skbuff[i];
240 dma_unmap_single(&lp->pci_dev->dev,
241 lp->rx_dma_addr[i],
242 lp->rx_buff_len - 2, DMA_FROM_DEVICE);
243 dev_kfree_skb(lp->rx_skbuff[i]);
244 lp->rx_skbuff[i] = NULL;
245 lp->rx_dma_addr[i] = 0;
257 struct amd8111e_priv *lp = netdev_priv(dev);
264 lp->rx_buff_len = mtu + ETH_HLEN + 10;
265 lp->options |= OPTION_JUMBO_ENABLE;
267 lp->rx_buff_len = PKT_BUFF_SZ;
268 lp->options &= ~OPTION_JUMBO_ENABLE;
279 struct amd8111e_priv *lp = netdev_priv(dev);
282 lp->rx_idx = lp->tx_idx = 0;
283 lp->tx_complete_idx = 0;
284 lp->tx_ring_idx = 0;
287 if (lp->opened)
293 lp->tx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
295 &lp->tx_ring_dma_addr, GFP_ATOMIC);
296 if (!lp->tx_ring)
299 lp->rx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
301 &lp->rx_ring_dma_addr, GFP_ATOMIC);
302 if (!lp->rx_ring)
312 lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len);
313 if (!lp->rx_skbuff[i]) {
316 dev_kfree_skb(lp->rx_skbuff[i]);
319 skb_reserve(lp->rx_skbuff[i], 2);
323 lp->rx_dma_addr[i] = dma_map_single(&lp->pci_dev->dev,
324 lp->rx_skbuff[i]->data,
325 lp->rx_buff_len - 2,
328 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
329 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
331 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
336 lp->tx_ring[i].buff_phy_addr = 0;
337 lp->tx_ring[i].tx_flags = 0;
338 lp->tx_ring[i].buff_count = 0;
345 dma_free_coherent(&lp->pci_dev->dev,
347 lp->rx_ring, lp->rx_ring_dma_addr);
351 dma_free_coherent(&lp->pci_dev->dev,
353 lp->tx_ring, lp->tx_ring_dma_addr);
367 struct amd8111e_priv *lp = netdev_priv(dev);
368 void __iomem *mmio = lp->mmio;
369 struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
423 struct amd8111e_priv *lp = netdev_priv(dev);
424 void __iomem *mmio = lp->mmio;
452 writel((u32)lp->tx_ring_dma_addr, mmio + XMT_RING_BASE_ADDR0);
453 writel((u32)lp->rx_ring_dma_addr, mmio + RCV_RING_BASE_ADDR0);
462 if (lp->options & OPTION_JUMBO_ENABLE) {
483 if (lp->options & OPTION_INTR_COAL_ENABLE) {
498 static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
502 void __iomem *mmio = lp->mmio;
509 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
573 if (lp->options & OPTION_JUMBO_ENABLE)
589 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
594 writel(INTREN, lp->mmio + CMD0);
597 intr0 = readl(lp->mmio + INT0);
598 writel(intr0, lp->mmio + INT0);
601 readl(lp->mmio + INT0);
606 static void amd8111e_stop_chip(struct amd8111e_priv *lp)
608 writel(RUN, lp->mmio + CMD0);
611 readl(lp->mmio + CMD0);
615 static void amd8111e_free_ring(struct amd8111e_priv *lp)
618 if (lp->rx_ring) {
619 dma_free_coherent(&lp->pci_dev->dev,
621 lp->rx_ring, lp->rx_ring_dma_addr);
622 lp->rx_ring = NULL;
625 if (lp->tx_ring) {
626 dma_free_coherent(&lp->pci_dev->dev,
628 lp->tx_ring, lp->tx_ring_dma_addr);
630 lp->tx_ring = NULL;
641 struct amd8111e_priv *lp = netdev_priv(dev);
645 while (lp->tx_complete_idx != lp->tx_idx) {
646 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
647 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
652 lp->tx_ring[tx_index].buff_phy_addr = 0;
655 if (lp->tx_skbuff[tx_index]) {
656 dma_unmap_single(&lp->pci_dev->dev,
657 lp->tx_dma_addr[tx_index],
658 lp->tx_skbuff[tx_index]->len,
660 dev_consume_skb_irq(lp->tx_skbuff[tx_index]);
661 lp->tx_skbuff[tx_index] = NULL;
662 lp->tx_dma_addr[tx_index] = 0;
664 lp->tx_complete_idx++;
666 lp->coal_conf.tx_packets++;
667 lp->coal_conf.tx_bytes +=
668 le16_to_cpu(lp->tx_ring[tx_index].buff_count);
671 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS + 2) {
673 /* lp->tx_full = 0; */
683 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
684 struct net_device *dev = lp->amd8111e_net_dev;
685 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
686 void __iomem *mmio = lp->mmio;
696 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
708 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
714 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
717 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
729 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
730 lp->drv_rx_errors++;
733 new_skb = netdev_alloc_skb(dev, lp->rx_buff_len);
738 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
739 lp->drv_rx_errors++;
744 skb = lp->rx_skbuff[rx_index];
745 dma_unmap_single(&lp->pci_dev->dev, lp->rx_dma_addr[rx_index],
746 lp->rx_buff_len - 2, DMA_FROM_DEVICE);
748 lp->rx_skbuff[rx_index] = new_skb;
749 lp->rx_dma_addr[rx_index] = dma_map_single(&lp->pci_dev->dev,
751 lp->rx_buff_len - 2,
758 u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info);
764 lp->coal_conf.rx_packets++;
765 lp->coal_conf.rx_bytes += pkt_len;
769 lp->rx_ring[rx_index].buff_phy_addr
770 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
771 lp->rx_ring[rx_index].buff_count =
772 cpu_to_le16(lp->rx_buff_len-2);
774 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
775 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
782 spin_lock_irqsave(&lp->lock, flags);
785 spin_unlock_irqrestore(&lp->lock, flags);
794 struct amd8111e_priv *lp = netdev_priv(dev);
798 status0 = readl(lp->mmio + STAT0);
802 lp->link_config.autoneg = AUTONEG_ENABLE;
804 lp->link_config.autoneg = AUTONEG_DISABLE;
807 lp->link_config.duplex = DUPLEX_FULL;
809 lp->link_config.duplex = DUPLEX_HALF;
812 lp->link_config.speed = SPEED_10;
814 lp->link_config.speed = SPEED_100;
817 (lp->link_config.speed == SPEED_100) ?
819 (lp->link_config.duplex == DUPLEX_FULL) ?
824 lp->link_config.speed = SPEED_INVALID;
825 lp->link_config.duplex = DUPLEX_INVALID;
826 lp->link_config.autoneg = AUTONEG_INVALID;
857 struct amd8111e_priv *lp = netdev_priv(dev);
858 void __iomem *mmio = lp->mmio;
862 if (!lp->opened)
864 spin_lock_irqsave(&lp->lock, flags);
888 lp->drv_rx_errors;
944 spin_unlock_irqrestore(&lp->lock, flags);
954 struct amd8111e_priv *lp = netdev_priv(dev);
955 struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
1081 struct amd8111e_priv *lp = netdev_priv(dev);
1082 void __iomem *mmio = lp->mmio;
1089 spin_lock(&lp->lock);
1110 if (napi_schedule_prep(&lp->napi)) {
1114 __napi_schedule(&lp->napi);
1137 spin_unlock(&lp->lock);
1159 struct amd8111e_priv *lp = netdev_priv(dev);
1162 napi_disable(&lp->napi);
1164 spin_lock_irq(&lp->lock);
1166 amd8111e_disable_interrupt(lp);
1167 amd8111e_stop_chip(lp);
1170 amd8111e_free_skbs(lp->amd8111e_net_dev);
1172 netif_carrier_off(lp->amd8111e_net_dev);
1175 if (lp->options & OPTION_DYN_IPG_ENABLE)
1176 timer_delete_sync(&lp->ipg_data.ipg_timer);
1178 spin_unlock_irq(&lp->lock);
1180 amd8111e_free_ring(lp);
1184 lp->opened = 0;
1193 struct amd8111e_priv *lp = netdev_priv(dev);
1199 napi_enable(&lp->napi);
1201 spin_lock_irq(&lp->lock);
1203 amd8111e_init_hw_default(lp);
1206 spin_unlock_irq(&lp->lock);
1207 napi_disable(&lp->napi);
1213 if (lp->options & OPTION_DYN_IPG_ENABLE) {
1214 add_timer(&lp->ipg_data.ipg_timer);
1218 lp->opened = 1;
1220 spin_unlock_irq(&lp->lock);
1230 static int amd8111e_tx_queue_avail(struct amd8111e_priv *lp)
1232 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1233 if (lp->tx_skbuff[tx_index])
1248 struct amd8111e_priv *lp = netdev_priv(dev);
1252 spin_lock_irqsave(&lp->lock, flags);
1254 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1256 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1258 lp->tx_skbuff[tx_index] = skb;
1259 lp->tx_ring[tx_index].tx_flags = 0;
1263 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1265 lp->tx_ring[tx_index].tag_ctrl_info =
1270 lp->tx_dma_addr[tx_index] =
1271 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
1273 lp->tx_ring[tx_index].buff_phy_addr =
1274 cpu_to_le32(lp->tx_dma_addr[tx_index]);
1278 lp->tx_ring[tx_index].tx_flags |=
1281 lp->tx_idx++;
1284 writel(VAL1 | TDMD0, lp->mmio + CMD0);
1285 writel(VAL2 | RDMD0, lp->mmio + CMD0);
1287 if (amd8111e_tx_queue_avail(lp) < 0) {
1290 spin_unlock_irqrestore(&lp->lock, flags);
1294 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1296 void __iomem *mmio = lp->mmio;
1320 struct amd8111e_priv *lp = netdev_priv(dev);
1325 writel(VAL2 | PROM, lp->mmio + CMD2);
1329 writel(PROM, lp->mmio + CMD2);
1334 lp->options |= OPTION_MULTICAST_ENABLE;
1335 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1341 lp->options &= ~OPTION_MULTICAST_ENABLE;
1342 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1344 writel(PROM, lp->mmio + CMD2);
1348 lp->options |= OPTION_MULTICAST_ENABLE;
1354 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1357 readl(lp->mmio + CMD2);
1364 struct amd8111e_priv *lp = netdev_priv(dev);
1365 struct pci_dev *pci_dev = lp->pci_dev;
1379 struct amd8111e_priv *lp = netdev_priv(dev);
1381 amd8111e_read_regs(lp, buf);
1387 struct amd8111e_priv *lp = netdev_priv(dev);
1388 spin_lock_irq(&lp->lock);
1389 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
1390 spin_unlock_irq(&lp->lock);
1397 struct amd8111e_priv *lp = netdev_priv(dev);
1399 spin_lock_irq(&lp->lock);
1400 res = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
1401 spin_unlock_irq(&lp->lock);
1407 struct amd8111e_priv *lp = netdev_priv(dev);
1408 return mii_nway_restart(&lp->mii_if);
1413 struct amd8111e_priv *lp = netdev_priv(dev);
1414 return mii_link_ok(&lp->mii_if);
1419 struct amd8111e_priv *lp = netdev_priv(dev);
1421 if (lp->options & OPTION_WOL_ENABLE)
1427 struct amd8111e_priv *lp = netdev_priv(dev);
1430 spin_lock_irq(&lp->lock);
1432 lp->options |=
1435 lp->options |=
1438 lp->options &= ~OPTION_WOL_ENABLE;
1439 spin_unlock_irq(&lp->lock);
1462 struct amd8111e_priv *lp = netdev_priv(dev);
1468 data->phy_id = lp->ext_phy_addr;
1473 spin_lock_irq(&lp->lock);
1474 err = amd8111e_read_phy(lp, data->phy_id,
1476 spin_unlock_irq(&lp->lock);
1483 spin_lock_irq(&lp->lock);
1484 err = amd8111e_write_phy(lp, data->phy_id,
1486 spin_unlock_irq(&lp->lock);
1498 struct amd8111e_priv *lp = netdev_priv(dev);
1503 spin_lock_irq(&lp->lock);
1506 writeb(dev->dev_addr[i], lp->mmio + PADR + i);
1508 spin_unlock_irq(&lp->lock);
1518 struct amd8111e_priv *lp = netdev_priv(dev);
1529 spin_lock_irq(&lp->lock);
1532 writel(RUN, lp->mmio + CMD0);
1537 spin_unlock_irq(&lp->lock);
1543 static int amd8111e_enable_magicpkt(struct amd8111e_priv *lp)
1545 writel(VAL1 | MPPLBA, lp->mmio + CMD3);
1546 writel(VAL0 | MPEN_SW, lp->mmio + CMD7);
1549 readl(lp->mmio + CMD7);
1553 static int amd8111e_enable_link_change(struct amd8111e_priv *lp)
1557 writel(VAL0 | LCMODE_SW, lp->mmio + CMD7);
1560 readl(lp->mmio + CMD7);
1571 struct amd8111e_priv *lp = netdev_priv(dev);
1576 spin_lock_irq(&lp->lock);
1578 spin_unlock_irq(&lp->lock);
1586 struct amd8111e_priv *lp = netdev_priv(dev);
1592 spin_lock_irq(&lp->lock);
1593 amd8111e_disable_interrupt(lp);
1594 spin_unlock_irq(&lp->lock);
1599 spin_lock_irq(&lp->lock);
1600 if (lp->options & OPTION_DYN_IPG_ENABLE)
1601 timer_delete_sync(&lp->ipg_data.ipg_timer);
1602 amd8111e_stop_chip(lp);
1603 spin_unlock_irq(&lp->lock);
1605 if (lp->options & OPTION_WOL_ENABLE) {
1607 if (lp->options & OPTION_WAKE_MAGIC_ENABLE)
1608 amd8111e_enable_magicpkt(lp);
1609 if (lp->options & OPTION_WAKE_PHY_ENABLE)
1610 amd8111e_enable_link_change(lp);
1624 struct amd8111e_priv *lp = netdev_priv(dev);
1631 spin_lock_irq(&lp->lock);
1634 if (lp->options & OPTION_DYN_IPG_ENABLE)
1635 mod_timer(&lp->ipg_data.ipg_timer,
1637 spin_unlock_irq(&lp->lock);
1644 struct amd8111e_priv *lp = timer_container_of(lp, t,
1646 struct ipg_info *ipg_data = &lp->ipg_data;
1647 void __iomem *mmio = lp->mmio;
1652 if (lp->link_config.duplex == DUPLEX_FULL) {
1698 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1705 struct amd8111e_priv *lp = netdev_priv(dev);
1711 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1713 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1715 lp->ext_phy_id = (id1 << 16) | id2;
1716 lp->ext_phy_addr = i;
1719 lp->ext_phy_id = 0;
1720 lp->ext_phy_addr = 1;
1744 struct amd8111e_priv *lp;
1797 lp = netdev_priv(dev);
1798 lp->pci_dev = pdev;
1799 lp->amd8111e_net_dev = dev;
1801 spin_lock_init(&lp->lock);
1803 lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len);
1804 if (!lp->mmio) {
1812 addr[i] = readb(lp->mmio + PADR + i);
1816 lp->ext_phy_option = speed_duplex[card_idx];
1818 lp->options |= OPTION_INTR_COAL_ENABLE;
1820 lp->options |= OPTION_DYN_IPG_ENABLE;
1830 netif_napi_add_weight(dev, &lp->napi, amd8111e_rx_poll, 32);
1836 lp->mii_if.dev = dev;
1837 lp->mii_if.mdio_read = amd8111e_mdio_read;
1838 lp->mii_if.mdio_write = amd8111e_mdio_write;
1839 lp->mii_if.phy_id = lp->ext_phy_addr;
1854 if (lp->options & OPTION_DYN_IPG_ENABLE) {
1855 timer_setup(&lp->ipg_data.ipg_timer, amd8111e_config_ipg, 0);
1856 lp->ipg_data.ipg_timer.expires = jiffies +
1858 lp->ipg_data.ipg = DEFAULT_IPG;
1859 lp->ipg_data.ipg_state = CSTATE;
1863 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000) >> 28;
1866 if (lp->ext_phy_id)
1868 lp->ext_phy_id, lp->ext_phy_addr);