ethernet/amd/7990.c

45 #define WRITERAP(lp, x)	out_be16(lp->base + LANCE_RAP, (x))
46 #define WRITERDP(lp, x)	out_be16(lp->base + LANCE_RDP, (x))
47 #define READRDP(lp)	in_be16(lp->base + LANCE_RDP)
59 #define WRITERAP(lp, x)	(lp->writerap(lp, x))
60 #define WRITERDP(lp, x)	(lp->writerdp(lp, x))
61 #define READRDP(lp)	(lp->readrdp(lp))
66 static inline void WRITERAP(struct lance_private *lp, __u16 value)
69 		out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
70 	} while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
73 static inline void WRITERDP(struct lance_private *lp, __u16 value)
76 		out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
77 	} while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
80 static inline __u16 READRDP(struct lance_private *lp)
84 		value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
85 	} while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
116 static void load_csrs(struct lance_private *lp)
118 	volatile struct lance_init_block *aib = lp->lance_init_block;
123 	WRITERAP(lp, LE_CSR1);                    /* load address of init block */
124 	WRITERDP(lp, leptr & 0xFFFF);
125 	WRITERAP(lp, LE_CSR2);
126 	WRITERDP(lp, leptr >> 16);
127 	WRITERAP(lp, LE_CSR3);
128 	WRITERDP(lp, lp->busmaster_regval);       /* set byteswap/ALEctrl/byte ctrl */
131 	WRITERAP(lp, LE_CSR0);
139 	struct lance_private *lp = netdev_priv(dev);
140 	volatile struct lance_init_block *ib = lp->init_block;
145 	aib = lp->lance_init_block;
147 	lp->rx_new = lp->tx_new = 0;
148 	lp->rx_old = lp->tx_old = 0;
177 	lp->tx_full = 0;
179 	for (i = 0; i < (1 << lp->lance_log_tx_bufs); i++) {
193 	for (i = 0; i < (1 << lp->lance_log_rx_bufs); i++) {
210 	ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
217 	ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
229 static int init_restart_lance(struct lance_private *lp)
233 	WRITERAP(lp, LE_CSR0);
234 	WRITERDP(lp, LE_C0_INIT);
239 	for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
241 	if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
242 		printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
247 	WRITERDP(lp, LE_C0_IDON);
248 	WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
255 	struct lance_private *lp = netdev_priv(dev);
259 	WRITERAP(lp, LE_CSR0);
260 	WRITERDP(lp, LE_C0_STOP);
262 	load_csrs(lp);
265 	status = init_restart_lance(lp);
274 	struct lance_private *lp = netdev_priv(dev);
275 	volatile struct lance_init_block *ib = lp->init_block;
285 		if (i == lp->rx_new)
297 	WRITERDP(lp, LE_C0_RINT | LE_C0_INEA);     /* ack Rx int, reenable ints */
298 	for (rd = &ib->brx_ring[lp->rx_new];     /* For each Rx ring we own... */
300 	     rd = &ib->brx_ring[lp->rx_new]) {
329 				lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
336 					 (unsigned char *)&(ib->rx_buf[lp->rx_new][0]),
347 		lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
354 	struct lance_private *lp = netdev_priv(dev);
355 	volatile struct lance_init_block *ib = lp->init_block;
364 	WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
367 	j = lp->tx_old;
368 	for (i = j; i != lp->tx_new; i = j) {
386 				if (lp->auto_select) {
387 					lp->tpe = 1 - lp->tpe;
390 					       lp->tpe ? "TPE" : "AUI");
392 					WRITERAP(lp, LE_CSR0);
393 					WRITERDP(lp, LE_C0_STOP);
395 					load_csrs(lp);
396 					init_restart_lance(lp);
409 				WRITERAP(lp, LE_CSR0);
410 				WRITERDP(lp, LE_C0_STOP);
412 				load_csrs(lp);
413 				init_restart_lance(lp);
433 		j = (j + 1) & lp->tx_ring_mod_mask;
435 	lp->tx_old = j;
436 	WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
444 	struct lance_private *lp = netdev_priv(dev);
447 	spin_lock(&lp->devlock);
449 	WRITERAP(lp, LE_CSR0);              /* LANCE Controller Status */
450 	csr0 = READRDP(lp);
455 		spin_unlock(&lp->devlock);
460 	WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
464 		WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
482 		WRITERDP(lp, LE_C0_STRT);
485 	if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
486 		lp->tx_full = 0;
490 	WRITERAP(lp, LE_CSR0);
491 	WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
493 	spin_unlock(&lp->devlock);
499 	struct lance_private *lp = netdev_priv(dev);
503 	if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
507 	spin_lock_init(&lp->devlock);
516 	struct lance_private *lp = netdev_priv(dev);
521 	WRITERAP(lp, LE_CSR0);
522 	WRITERDP(lp, LE_C0_STOP);
524 	free_irq(lp->irq, dev);
541 	struct lance_private *lp = netdev_priv(dev);
542 	volatile struct lance_init_block *ib = lp->init_block;
569 	entry = lp->tx_new & lp->tx_ring_mod_mask;
579 	lp->tx_new = (lp->tx_new + 1) & lp->tx_ring_mod_mask;
583 	WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
586 	spin_lock_irqsave(&lp->devlock, flags);
590 		lp->tx_full = 1;
591 	spin_unlock_irqrestore(&lp->devlock, flags);
600 	struct lance_private *lp = netdev_priv(dev);
601 	volatile struct lance_init_block *ib = lp->init_block;
627 	struct lance_private *lp = netdev_priv(dev);
628 	volatile struct lance_init_block *ib = lp->init_block;
635 	while (lp->tx_old != lp->tx_new)
638 	WRITERAP(lp, LE_CSR0);
639 	WRITERDP(lp, LE_C0_STOP);
648 	load_csrs(lp);
649 	init_restart_lance(lp);
659 	struct lance_private *lp = netdev_priv(dev);
661 	spin_lock(&lp->devlock);
662 	WRITERAP(lp, LE_CSR0);
663 	WRITERDP(lp, LE_C0_STRT);
664 	spin_unlock(&lp->devlock);