Lines Matching full:qdma
41 struct airoha_qdma *qdma = irq_bank->qdma;
42 int bank = irq_bank - &qdma->irq_banks[0];
52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),
57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));
76 struct airoha_eth *eth = port->qdma->eth;
107 struct airoha_eth *eth = port->qdma->eth;
504 /* QDMA LAN, RX Ring-22 */
554 struct airoha_qdma *qdma = q->qdma;
555 int qid = q - &qdma->q_rx[0];
588 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),
619 struct airoha_qdma *qdma = q->qdma;
620 struct airoha_eth *eth = qdma->eth;
621 int qid = q - &qdma->q_rx[0];
731 struct airoha_qdma *qdma = q->qdma;
732 int i, qid = q - &qdma->q_rx[0];
736 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
740 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg,
749 struct airoha_qdma *qdma, int ndesc)
758 .dev = qdma->eth->dev,
761 struct airoha_eth *eth = qdma->eth;
762 int qid = q - &qdma->q_rx[0], thr;
767 q->qdma = qdma;
789 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr);
790 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid),
795 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK,
797 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
799 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK);
808 struct airoha_eth *eth = q->qdma->eth;
822 static int airoha_qdma_init_rx(struct airoha_qdma *qdma)
826 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
834 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma,
847 struct airoha_qdma *qdma;
852 qdma = irq_q->qdma;
853 id = irq_q - &qdma->q_tx_irq[0];
854 eth = qdma->eth;
856 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id));
878 if (qid >= ARRAY_SIZE(qdma->q_tx))
881 q = &qdma->q_tx[qid];
939 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id),
941 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id),
946 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
953 struct airoha_qdma *qdma, int size)
955 struct airoha_eth *eth = qdma->eth;
956 int i, qid = q - &qdma->q_tx[0];
961 q->qdma = qdma;
982 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid),
985 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr);
986 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
988 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK,
995 struct airoha_qdma *qdma, int size)
997 int id = irq_q - &qdma->q_tx_irq[0];
998 struct airoha_eth *eth = qdma->eth;
1010 irq_q->qdma = qdma;
1012 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr);
1013 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK,
1015 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK,
1021 static int airoha_qdma_init_tx(struct airoha_qdma *qdma)
1025 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
1026 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma,
1032 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1033 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma,
1044 struct airoha_eth *eth = q->qdma->eth;
1061 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
1064 struct airoha_eth *eth = qdma->eth;
1065 int id = qdma - ð->qdma[0];
1070 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
1103 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
1109 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
1111 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,
1114 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK,
1116 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG,
1124 30 * USEC_PER_MSEC, true, qdma,
1128 static void airoha_qdma_init_qos(struct airoha_qdma *qdma)
1130 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK);
1131 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK);
1133 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG,
1136 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG,
1140 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG,
1143 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG,
1148 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK);
1150 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK,
1152 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK,
1155 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK);
1156 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK,
1158 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG,
1162 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK);
1163 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG,
1165 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK,
1167 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG,
1171 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK);
1172 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK,
1174 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK,
1178 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma)
1184 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0);
1185 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
1190 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0);
1191 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
1199 static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
1203 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
1205 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff);
1207 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0,
1209 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1,
1211 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2,
1213 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3,
1217 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
1219 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4,
1223 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1224 if (!qdma->q_tx[i].ndesc)
1228 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i),
1231 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i),
1235 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG,
1245 airoha_qdma_init_qos(qdma);
1247 /* disable qdma rx delay interrupt */
1248 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1249 if (!qdma->q_rx[i].ndesc)
1252 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i),
1256 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG,
1258 airoha_qdma_init_qos_stats(qdma);
1266 struct airoha_qdma *qdma = irq_bank->qdma;
1272 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i));
1274 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]);
1277 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state))
1292 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) {
1293 if (!qdma->q_rx[i].ndesc)
1297 napi_schedule(&qdma->q_rx[i].napi);
1301 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
1307 napi_schedule(&qdma->q_tx_irq[i].napi);
1315 struct airoha_qdma *qdma)
1317 struct airoha_eth *eth = qdma->eth;
1318 int i, id = qdma - ð->qdma[0];
1320 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
1321 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i];
1326 irq_bank->qdma = qdma;
1349 struct airoha_qdma *qdma)
1351 int err, id = qdma - ð->qdma[0];
1354 qdma->eth = eth;
1355 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id);
1359 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res);
1360 if (IS_ERR(qdma->regs))
1361 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs),
1362 "failed to iomap qdma%d regs\n", id);
1364 err = airoha_qdma_init_irq_banks(pdev, qdma);
1368 err = airoha_qdma_init_rx(qdma);
1372 err = airoha_qdma_init_tx(qdma);
1376 err = airoha_qdma_init_hfwd_queues(qdma);
1380 return airoha_qdma_hw_init(qdma);
1408 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
1409 err = airoha_qdma_init(pdev, eth, ð->qdma[i]);
1423 static void airoha_hw_cleanup(struct airoha_qdma *qdma)
1427 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1428 if (!qdma->q_rx[i].ndesc)
1431 netif_napi_del(&qdma->q_rx[i].napi);
1432 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]);
1433 if (qdma->q_rx[i].page_pool)
1434 page_pool_destroy(qdma->q_rx[i].page_pool);
1437 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1438 netif_napi_del(&qdma->q_tx_irq[i].napi);
1440 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1441 if (!qdma->q_tx[i].ndesc)
1444 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
1448 static void airoha_qdma_start_napi(struct airoha_qdma *qdma)
1452 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1453 napi_enable(&qdma->q_tx_irq[i].napi);
1455 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1456 if (!qdma->q_rx[i].ndesc)
1459 napi_enable(&qdma->q_rx[i].napi);
1463 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma)
1467 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1468 napi_disable(&qdma->q_tx_irq[i].napi);
1470 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1471 if (!qdma->q_rx[i].ndesc)
1474 napi_disable(&qdma->q_rx[i].napi);
1480 struct airoha_eth *eth = port->qdma->eth;
1626 struct airoha_qdma *qdma = port->qdma;
1634 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
1637 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
1640 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id),
1645 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
1648 atomic_inc(&qdma->users);
1656 struct airoha_qdma *qdma = port->qdma;
1664 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++)
1667 if (atomic_dec_and_test(&qdma->users)) {
1668 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
1672 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1673 if (!qdma->q_tx[i].ndesc)
1676 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
1700 struct airoha_eth *eth = port->qdma->eth;
1750 struct airoha_eth *eth = port->qdma->eth;
1800 struct airoha_eth *eth = port->qdma->eth;
1877 struct airoha_qdma *qdma = port->qdma;
1886 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx);
1917 q = &qdma->q_tx[qid];
1977 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid),
2007 struct airoha_eth *eth = port->qdma->eth;
2076 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel),
2083 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG,
2091 true, port->qdma,
2097 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3),
2163 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma,
2165 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma,
2201 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id,
2210 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2213 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma,
2217 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr));
2219 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr));
2224 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id,
2234 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val);
2235 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2240 qdma, REG_TRTCM_CFG_PARAM(addr));
2243 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id,
2249 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE,
2256 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE,
2260 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma,
2267 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2272 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG);
2289 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2299 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2303 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id,
2311 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2316 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2320 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel,
2331 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2335 qdma, REG_TRTCM_CFG_PARAM(addr)))
2338 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr));
2340 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr));
2345 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel,
2356 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val);
2357 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2362 qdma, REG_TRTCM_CFG_PARAM(addr));
2365 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel,
2371 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2377 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2381 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma,
2389 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2393 val = airoha_qdma_rr(qdma, addr);
2410 err = airoha_qdma_set_trtcm_param(qdma, channel, addr,
2418 return airoha_qdma_set_trtcm_param(qdma, channel, addr,
2430 err = airoha_qdma_set_trtcm_config(port->qdma, channel,
2436 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel,
2488 struct airoha_qdma *qdma = port->qdma;
2491 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
2494 if (!qdma->q_rx[i].ndesc)
2497 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type);
2501 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate,
2815 struct airoha_qdma *qdma;
2846 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA];
2858 dev->irq = qdma->irq_banks[0].irq;
2879 port->qdma = qdma;
2924 eth->rsts[2].id = "qdma";
2959 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2960 airoha_qdma_start_napi(ð->qdma[i]);
2980 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2981 airoha_qdma_stop_napi(ð->qdma[i]);
2984 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2985 airoha_hw_cleanup(ð->qdma[i]);
3006 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
3007 airoha_qdma_stop_napi(ð->qdma[i]);
3008 airoha_hw_cleanup(ð->qdma[i]);