Lines Matching defs:chip
3 * Marvell 88e6xxx Ethernet switch single-chip support
36 #include "chip.h"
47 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 dev_err(chip->dev, "Switch registers lock not held!\n");
55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
59 assert_reg_lock(chip);
61 err = mv88e6xxx_smi_read(chip, addr, reg, val);
65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
75 assert_reg_lock(chip);
77 err = mv88e6xxx_smi_write(chip, addr, reg, val);
81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
100 err = mv88e6xxx_read(chip, addr, reg, &data);
113 err = mv88e6xxx_read(chip, addr, reg, &data);
120 dev_err(chip->dev, "Timeout while waiting for switch\n");
124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
135 mdio_bus = list_first_entry_or_null(&chip->mdios,
145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
148 chip->g1_irq.masked |= (1 << n);
153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
156 chip->g1_irq.masked &= ~(1 << n);
159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
168 mv88e6xxx_reg_lock(chip);
169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
170 mv88e6xxx_reg_unlock(chip);
176 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
178 sub_irq = irq_find_mapping(chip->g1_irq.domain,
185 mv88e6xxx_reg_lock(chip);
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
191 mv88e6xxx_reg_unlock(chip);
194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
203 struct mv88e6xxx_chip *chip = dev_id;
205 return mv88e6xxx_g1_irq_thread_work(chip);
210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
212 mv88e6xxx_reg_lock(chip);
217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
227 reg |= (~chip->g1_irq.masked & mask);
229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
234 mv88e6xxx_reg_unlock(chip);
249 struct mv88e6xxx_chip *chip = d->host_data;
252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
274 virq = irq_find_mapping(chip->g1_irq.domain, irq);
278 irq_domain_remove(chip->g1_irq.domain);
281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
287 free_irq(chip->irq, chip);
289 mv88e6xxx_reg_lock(chip);
290 mv88e6xxx_g1_irq_free_common(chip);
291 mv88e6xxx_reg_unlock(chip);
294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
299 chip->g1_irq.nirqs = chip->info->g1_irqs;
300 chip->g1_irq.domain = irq_domain_create_simple(
301 NULL, chip->g1_irq.nirqs, 0,
302 &mv88e6xxx_g1_irq_domain_ops, chip);
303 if (!chip->g1_irq.domain)
306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
307 irq_create_mapping(chip->g1_irq.domain, irq);
309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
310 chip->g1_irq.masked = ~0;
312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
335 virq = irq_find_mapping(chip->g1_irq.domain, irq);
339 irq_domain_remove(chip->g1_irq.domain);
344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
350 err = mv88e6xxx_g1_irq_setup_common(chip);
358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
360 snprintf(chip->irq_name, sizeof(chip->irq_name),
361 "mv88e6xxx-%s", dev_name(chip->dev));
363 mv88e6xxx_reg_unlock(chip);
364 err = request_threaded_irq(chip->irq, NULL,
367 chip->irq_name, chip);
368 mv88e6xxx_reg_lock(chip);
370 mv88e6xxx_g1_irq_free_common(chip);
377 struct mv88e6xxx_chip *chip = container_of(work,
380 mv88e6xxx_g1_irq_thread_work(chip);
382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
390 err = mv88e6xxx_g1_irq_setup_common(chip);
394 kthread_init_delayed_work(&chip->irq_poll_work,
397 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev));
398 if (IS_ERR(chip->kworker))
399 return PTR_ERR(chip->kworker);
401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
410 kthread_destroy_worker(chip->kworker);
412 mv88e6xxx_reg_lock(chip);
413 mv88e6xxx_g1_irq_free_common(chip);
414 mv88e6xxx_reg_unlock(chip);
417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
422 if (chip->info->ops->port_set_rgmii_delay) {
423 err = chip->info->ops->port_set_rgmii_delay(chip, port,
429 if (chip->info->ops->port_set_cmode) {
430 err = chip->info->ops->port_set_cmode(chip, port,
439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
445 if (!chip->info->ops->port_set_link)
449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
453 if (chip->info->ops->port_set_speed_duplex) {
454 err = chip->info->ops->port_set_speed_duplex(chip, port,
460 if (chip->info->ops->port_set_pause) {
461 err = chip->info->ops->port_set_pause(chip, port, pause);
466 err = mv88e6xxx_port_config_interface(chip, port, mode);
468 if (chip->info->ops->port_set_link(chip, port, link))
469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
476 return port >= chip->info->internal_phys_offset &&
477 port < chip->info->num_internal_phys +
478 chip->info->internal_phys_offset;
481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
489 if (chip->info->family == MV88E6XXX_FAMILY_6250)
490 return mv88e6xxx_phy_is_internal(chip, port);
492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
494 dev_err(chip->dev,
513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
516 u8 cmode = chip->ports[port].cmode;
520 if (mv88e6xxx_phy_is_internal(chip, port)) {
532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
535 u8 cmode = chip->ports[port].cmode;
571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
580 dev_err(chip->dev, "p%d: failed to read port status\n", port);
614 dev_err(chip->dev,
620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
623 if (!mv88e6xxx_phy_is_internal(chip, port))
624 mv88e6250_setup_supported_interfaces(chip, port, config);
629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port)
646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val);
659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val);
664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
687 dev_err(chip->dev, "p%d: failed to read scratch\n",
692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
773 mv88e6390_phylink_get_caps(chip, port, config);
803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
850 struct mv88e6xxx_chip *chip = ds->priv;
852 mv88e6xxx_reg_lock(chip);
853 chip->info->ops->phylink_get_caps(chip, port, config);
854 mv88e6xxx_reg_unlock(chip);
856 if (mv88e6xxx_phy_is_internal(chip, port)) {
870 struct mv88e6xxx_chip *chip = dp->ds->priv;
873 if (chip->info->ops->pcs_ops)
874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index,
884 struct mv88e6xxx_chip *chip = dp->ds->priv;
893 chip->ports[port].interface != interface &&
894 chip->info->ops->port_set_link) {
895 mv88e6xxx_reg_lock(chip);
896 err = chip->info->ops->port_set_link(chip, port,
898 mv88e6xxx_reg_unlock(chip);
909 struct mv88e6xxx_chip *chip = dp->ds->priv;
913 mv88e6xxx_reg_lock(chip);
915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
916 err = mv88e6xxx_port_config_interface(chip, port,
923 mv88e6xxx_reg_unlock(chip);
926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port);
933 struct mv88e6xxx_chip *chip = dp->ds->priv;
943 mv88e6xxx_reg_lock(chip);
945 if (chip->info->ops->port_set_link &&
947 chip->ports[port].interface != interface) ||
948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
951 mv88e6xxx_reg_unlock(chip);
953 chip->ports[port].interface = interface;
963 struct mv88e6xxx_chip *chip = dp->ds->priv;
968 ops = chip->info->ops;
970 mv88e6xxx_reg_lock(chip);
974 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
976 err = ops->port_sync_link(chip, port, mode, false);
979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
981 mv88e6xxx_reg_unlock(chip);
984 dev_err(chip->dev,
995 struct mv88e6xxx_chip *chip = dp->ds->priv;
1000 ops = chip->info->ops;
1002 mv88e6xxx_reg_lock(chip);
1007 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
1010 err = ops->port_set_speed_duplex(chip, port,
1017 err = ops->port_sync_link(chip, port, mode, true);
1020 mv88e6xxx_reg_unlock(chip);
1023 dev_err(chip->dev,
1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1031 if (!chip->info->ops->stats_snapshot)
1034 mv88e6xxx_reg_lock(chip);
1035 err = chip->info->ops->stats_snapshot(chip, port);
1036 mv88e6xxx_reg_unlock(chip);
1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1145 mv88e6xxx_g1_stats_read(chip, reg, &low);
1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1156 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1169 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1172 mv88e6xxx_stats_get_strings(chip, data,
1176 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1182 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1185 mv88e6xxx_stats_get_strings(chip, data,
1208 struct mv88e6xxx_chip *chip = ds->priv;
1213 mv88e6xxx_reg_lock(chip);
1215 if (chip->info->ops->stats_get_strings)
1216 chip->info->ops->stats_get_strings(chip, &data);
1218 if (chip->info->ops->serdes_get_strings)
1219 chip->info->ops->serdes_get_strings(chip, port, &data);
1223 mv88e6xxx_reg_unlock(chip);
1226 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1240 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1246 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1251 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1259 struct mv88e6xxx_chip *chip = ds->priv;
1266 mv88e6xxx_reg_lock(chip);
1267 if (chip->info->ops->stats_get_sset_count)
1268 count = chip->info->ops->stats_get_sset_count(chip);
1272 if (chip->info->ops->serdes_get_sset_count)
1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1283 mv88e6xxx_reg_unlock(chip);
1288 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1292 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1297 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1301 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1306 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1310 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1316 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1320 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1326 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1332 if (!(stat->type & chip->info->stats_type))
1335 if (chip->info->ops->stats_get_stat) {
1336 mv88e6xxx_reg_lock(chip);
1337 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1338 mv88e6xxx_reg_unlock(chip);
1344 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1352 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1357 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1360 *data++ = chip->ports[port].atu_member_violation;
1361 *data++ = chip->ports[port].atu_miss_violation;
1362 *data++ = chip->ports[port].atu_full_violation;
1363 *data++ = chip->ports[port].vtu_member_violation;
1364 *data++ = chip->ports[port].vtu_miss_violation;
1367 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1372 count = mv88e6xxx_stats_get_stats(chip, port, data);
1374 mv88e6xxx_reg_lock(chip);
1375 if (chip->info->ops->serdes_get_stats) {
1377 count = chip->info->ops->serdes_get_stats(chip, port, data);
1380 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1381 mv88e6xxx_reg_unlock(chip);
1387 struct mv88e6xxx_chip *chip = ds->priv;
1390 ret = mv88e6xxx_stats_snapshot(chip, port);
1394 mv88e6xxx_get_stats(chip, port, data);
1400 struct mv88e6xxx_chip *chip = ds->priv;
1403 ret = mv88e6xxx_stats_snapshot(chip, port);
1408 mv88e6xxx_stats_get_stat(chip, port, \
1448 struct mv88e6xxx_chip *chip = ds->priv;
1451 ret = mv88e6xxx_stats_snapshot(chip, port);
1456 mv88e6xxx_stats_get_stat(chip, port, \
1478 struct mv88e6xxx_chip *chip = ds->priv;
1482 if (chip->info->ops->serdes_get_regs_len)
1483 len += chip->info->ops->serdes_get_regs_len(chip, port);
1491 struct mv88e6xxx_chip *chip = ds->priv;
1497 regs->version = chip->info->prod_num;
1501 mv88e6xxx_reg_lock(chip);
1505 err = mv88e6xxx_port_read(chip, port, i, ®);
1510 if (chip->info->ops->serdes_get_regs)
1511 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1513 mv88e6xxx_reg_unlock(chip);
1524 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1526 struct dsa_switch *ds = chip->ds;
1566 return mv88e6xxx_port_mask(chip);
1589 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1591 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1596 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1602 struct mv88e6xxx_chip *chip = ds->priv;
1605 mv88e6xxx_reg_lock(chip);
1606 err = mv88e6xxx_port_set_state(chip, port, state);
1607 mv88e6xxx_reg_unlock(chip);
1613 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1617 if (chip->info->ops->ieee_pri_map) {
1618 err = chip->info->ops->ieee_pri_map(chip);
1623 if (chip->info->ops->ip_pri_map) {
1624 err = chip->info->ops->ip_pri_map(chip);
1632 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1634 struct dsa_switch *ds = chip->ds;
1638 if (!chip->info->global2_addr)
1647 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1652 if (chip->info->ops->set_cascade_port) {
1654 err = chip->info->ops->set_cascade_port(chip, port);
1659 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1666 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1669 if (chip->info->global2_addr)
1670 return mv88e6xxx_g2_trunk_clear(chip);
1675 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1677 if (chip->info->ops->rmu_disable)
1678 return chip->info->ops->rmu_disable(chip);
1683 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1685 if (chip->info->ops->pot_clear)
1686 return chip->info->ops->pot_clear(chip);
1691 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1693 if (chip->info->ops->mgmt_rsvd2cpu)
1694 return chip->info->ops->mgmt_rsvd2cpu(chip);
1699 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1703 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1712 if (chip->info->ops->port_setup_message_port) {
1713 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1718 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1721 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1726 if (!chip->info->ops->irl_init_all)
1729 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1733 err = chip->info->ops->irl_init_all(chip, port);
1741 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1743 if (chip->info->ops->set_switch_mac) {
1748 return chip->info->ops->set_switch_mac(chip, addr);
1754 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1756 struct dsa_switch_tree *dst = chip->ds->dst;
1761 if (!mv88e6xxx_has_pvt(chip))
1764 /* Skip the local source device, which uses in-chip port VLAN */
1765 if (dev != chip->ds->index) {
1766 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1783 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1786 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1791 if (!mv88e6xxx_has_pvt(chip))
1797 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1803 err = mv88e6xxx_pvt_map(chip, dev, port);
1812 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1815 if (dsa_to_port(chip->ds, port)->lag)
1822 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1827 struct mv88e6xxx_chip *chip = ds->priv;
1830 mv88e6xxx_reg_lock(chip);
1831 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1832 mv88e6xxx_reg_unlock(chip);
1835 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1839 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1841 if (!mv88e6xxx_max_vid(chip))
1844 return mv88e6xxx_g1_vtu_flush(chip);
1847 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1852 if (!chip->info->ops->vtu_getnext)
1857 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1860 err = chip->info->ops->vtu_getnext(chip, entry);
1868 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1869 int (*cb)(struct mv88e6xxx_chip *chip,
1875 .vid = mv88e6xxx_max_vid(chip),
1880 if (!chip->info->ops->vtu_getnext)
1884 err = chip->info->ops->vtu_getnext(chip, &entry);
1891 err = cb(chip, &entry, priv);
1894 } while (entry.vid < mv88e6xxx_max_vid(chip));
1899 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1902 if (!chip->info->ops->vtu_loadpurge)
1905 return chip->info->ops->vtu_loadpurge(chip, entry);
1908 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1910 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID);
1911 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1915 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1918 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1921 if (!chip->info->ops->stu_loadpurge)
1924 return chip->info->ops->stu_loadpurge(chip, entry);
1927 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1934 if (!mv88e6xxx_has_stu(chip))
1942 return mv88e6xxx_stu_loadpurge(chip, &stu);
1945 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1952 list_for_each_entry(mst, &chip->msts, node)
1957 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1960 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1969 * If the chip lacks STU support, numerically the "sid" variable will
1974 if (!mv88e6xxx_has_stu(chip) || !sid)
1977 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1985 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1999 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
2005 if (!mv88e6xxx_has_stu(chip)) {
2015 list_for_each_entry(mst, &chip->msts, node) {
2023 err = mv88e6xxx_sid_get(chip, sid);
2045 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2046 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2050 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2054 list_add_tail(&mst->node, &chip->msts);
2067 struct mv88e6xxx_chip *chip = ds->priv;
2072 if (!mv88e6xxx_has_stu(chip))
2091 list_for_each_entry(mst, &chip->msts, node) {
2098 mv88e6xxx_reg_lock(chip);
2099 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2100 mv88e6xxx_reg_unlock(chip);
2112 struct mv88e6xxx_chip *chip = ds->priv;
2120 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2149 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2151 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2153 struct mv88e6xxx_port *p = &chip->ports[port];
2167 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2171 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2178 struct mv88e6xxx_chip *chip = ds->priv;
2183 if (!mv88e6xxx_max_vid(chip))
2186 mv88e6xxx_reg_lock(chip);
2188 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2192 err = mv88e6xxx_port_commit_pvid(chip, port);
2197 mv88e6xxx_reg_unlock(chip);
2206 struct mv88e6xxx_chip *chip = ds->priv;
2209 if (!mv88e6xxx_max_vid(chip))
2215 mv88e6xxx_reg_lock(chip);
2217 mv88e6xxx_reg_unlock(chip);
2222 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip,
2239 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2254 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry);
2257 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip,
2264 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2271 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2279 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry);
2303 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2306 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2317 if (!chip->info->ops->port_set_policy)
2334 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2345 idr_for_each_entry(&chip->policies, policy, id)
2351 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2354 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2400 idr_for_each_entry(&chip->policies, policy, id) {
2407 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2412 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2415 devm_kfree(chip->dev, policy);
2426 err = mv88e6xxx_policy_apply(chip, port, policy);
2428 idr_remove(&chip->policies, fs->location);
2429 devm_kfree(chip->dev, policy);
2440 struct mv88e6xxx_chip *chip = ds->priv;
2445 mv88e6xxx_reg_lock(chip);
2452 idr_for_each_entry(&chip->policies, policy, id)
2459 policy = idr_find(&chip->policies, fs->location);
2468 idr_for_each_entry(&chip->policies, policy, id)
2478 mv88e6xxx_reg_unlock(chip);
2487 struct mv88e6xxx_chip *chip = ds->priv;
2491 mv88e6xxx_reg_lock(chip);
2495 err = mv88e6xxx_policy_insert(chip, port, fs);
2499 policy = idr_remove(&chip->policies, fs->location);
2502 err = mv88e6xxx_policy_apply(chip, port, policy);
2503 devm_kfree(chip->dev, policy);
2511 mv88e6xxx_reg_unlock(chip);
2516 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2524 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2527 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2532 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2533 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2536 if (dsa_is_unused_port(chip->ds, port))
2546 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2560 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2575 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2579 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2592 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2597 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2601 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2608 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2618 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2622 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2631 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2635 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2641 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2645 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2650 bitmap_set(chip->fid_bitmap, vlan.fid, 1);
2659 struct mv88e6xxx_chip *chip = ds->priv;
2662 struct mv88e6xxx_port *p = &chip->ports[port];
2686 mv88e6xxx_reg_lock(chip);
2688 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2699 err = mv88e6xxx_port_commit_pvid(chip, port);
2706 err = mv88e6xxx_port_commit_pvid(chip, port);
2712 mv88e6xxx_reg_unlock(chip);
2717 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2726 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2741 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2749 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2754 err = mv88e6xxx_mst_put(chip, vlan.sid);
2759 bitmap_clear(chip->fid_bitmap, vlan.fid, 1);
2762 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2768 struct mv88e6xxx_chip *chip = ds->priv;
2769 struct mv88e6xxx_port *p = &chip->ports[port];
2773 if (!mv88e6xxx_max_vid(chip))
2783 mv88e6xxx_reg_lock(chip);
2785 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2789 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2796 err = mv88e6xxx_port_commit_pvid(chip, port);
2802 mv88e6xxx_reg_unlock(chip);
2809 struct mv88e6xxx_chip *chip = ds->priv;
2813 mv88e6xxx_reg_lock(chip);
2815 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2819 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2822 mv88e6xxx_reg_unlock(chip);
2831 struct mv88e6xxx_chip *chip = ds->priv;
2836 if (!mv88e6xxx_has_stu(chip))
2839 mv88e6xxx_reg_lock(chip);
2841 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2852 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2859 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2861 mv88e6xxx_mst_put(chip, new_sid);
2866 err = mv88e6xxx_mst_put(chip, old_sid);
2869 mv88e6xxx_reg_unlock(chip);
2877 struct mv88e6xxx_chip *chip = ds->priv;
2880 mv88e6xxx_reg_lock(chip);
2881 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2886 if (!mv88e6xxx_port_db_find(chip, addr, vid))
2890 mv88e6xxx_reg_unlock(chip);
2899 struct mv88e6xxx_chip *chip = ds->priv;
2902 mv88e6xxx_reg_lock(chip);
2903 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2904 mv88e6xxx_reg_unlock(chip);
2909 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2921 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2950 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2956 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2960 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2972 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2976 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2980 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2986 struct mv88e6xxx_chip *chip = ds->priv;
2989 mv88e6xxx_reg_lock(chip);
2990 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2991 mv88e6xxx_reg_unlock(chip);
2996 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2999 struct dsa_switch *ds = chip->ds;
3010 err = mv88e6xxx_port_vlan_map(chip, dp->index);
3015 * remap its cross-chip Port VLAN Table entry.
3017 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
3036 struct mv88e6xxx_chip *chip = ds->priv;
3038 return mv88e6xxx_pvt_map(chip, dev, 0);
3046 struct mv88e6xxx_chip *chip = ds->priv;
3049 mv88e6xxx_reg_lock(chip);
3051 err = mv88e6xxx_bridge_map(chip, bridge);
3055 err = mv88e6xxx_port_set_map_da(chip, port, true);
3059 err = mv88e6xxx_port_commit_pvid(chip, port);
3063 if (mv88e6xxx_has_pvt(chip)) {
3072 mv88e6xxx_reg_unlock(chip);
3080 struct mv88e6xxx_chip *chip = ds->priv;
3083 mv88e6xxx_reg_lock(chip);
3087 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3089 if (mv88e6xxx_bridge_map(chip, bridge) ||
3090 mv88e6xxx_port_vlan_map(chip, port))
3091 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3093 err = mv88e6xxx_port_set_map_da(chip, port, false);
3099 err = mv88e6xxx_port_commit_pvid(chip, port);
3105 mv88e6xxx_reg_unlock(chip);
3113 struct mv88e6xxx_chip *chip = ds->priv;
3119 mv88e6xxx_reg_lock(chip);
3120 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3122 mv88e6xxx_reg_unlock(chip);
3131 struct mv88e6xxx_chip *chip = ds->priv;
3136 mv88e6xxx_reg_lock(chip);
3137 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3139 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3140 mv88e6xxx_reg_unlock(chip);
3143 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3145 if (chip->info->ops->reset)
3146 return chip->info->ops->reset(chip);
3151 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3153 struct gpio_desc *gpiod = chip->reset;
3167 if (chip->info->ops->hardware_reset_pre) {
3168 err = chip->info->ops->hardware_reset_pre(chip);
3170 dev_err(chip->dev, "pre-reset error: %d\n", err);
3178 if (chip->info->ops->hardware_reset_post) {
3179 err = chip->info->ops->hardware_reset_post(chip);
3181 dev_err(chip->dev, "post-reset error: %d\n", err);
3186 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3191 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3192 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3205 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3209 err = mv88e6xxx_disable_ports(chip);
3213 mv88e6xxx_hardware_reset(chip);
3215 return mv88e6xxx_software_reset(chip);
3218 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3224 if (!chip->info->ops->port_set_frame_mode)
3227 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3231 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3235 if (chip->info->ops->port_set_ether_type)
3236 return chip->info->ops->port_set_ether_type(chip, port, etype);
3241 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3243 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3248 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3250 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3255 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3257 return mv88e6xxx_set_port_mode(chip, port,
3263 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3265 if (dsa_is_dsa_port(chip->ds, port))
3266 return mv88e6xxx_set_port_mode_dsa(chip, port);
3268 if (dsa_is_user_port(chip->ds, port))
3269 return mv88e6xxx_set_port_mode_normal(chip, port);
3272 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3273 return mv88e6xxx_set_port_mode_dsa(chip, port);
3275 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3276 return mv88e6xxx_set_port_mode_edsa(chip, port);
3281 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3283 bool message = dsa_is_dsa_port(chip->ds, port);
3285 return mv88e6xxx_port_set_message_port(chip, port, message);
3288 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3292 if (chip->info->ops->port_set_ucast_flood) {
3293 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3297 if (chip->info->ops->port_set_mcast_flood) {
3298 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3306 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3312 if (!chip->info->ops->set_egress_port)
3315 err = chip->info->ops->set_egress_port(chip, direction, port);
3320 chip->ingress_dest_port = port;
3322 chip->egress_dest_port = port;
3327 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3329 struct dsa_switch *ds = chip->ds;
3334 if (chip->info->ops->port_set_upstream_port) {
3335 err = chip->info->ops->port_set_upstream_port(chip, port,
3342 if (chip->info->ops->set_cpu_port) {
3343 err = chip->info->ops->set_cpu_port(chip,
3349 err = mv88e6xxx_set_egress_port(chip,
3355 err = mv88e6xxx_set_egress_port(chip,
3365 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3370 struct dsa_switch *ds = chip->ds;
3378 p = &chip->ports[port];
3379 p->chip = chip;
3383 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports");
3385 ports_fwnode = device_get_named_child_node(chip->dev, "ports");
3398 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n");
3401 if (chip->info->ops->port_setup_leds) {
3402 err = chip->info->ops->port_setup_leds(chip, port);
3407 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3435 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3439 err = mv88e6xxx_setup_port_mode(chip, port);
3443 err = mv88e6xxx_setup_egress_floods(chip, port);
3454 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3458 err = mv88e6xxx_setup_upstream_port(chip, port);
3470 chip->info->ops->port_set_policy) {
3471 err = chip->info->ops->port_set_policy(chip, port,
3483 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3497 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3511 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3517 if (chip->info->ops->port_set_jumbo_size) {
3518 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3538 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3544 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3549 if (chip->info->ops->port_pause_limit) {
3550 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3555 if (chip->info->ops->port_disable_learn_limit) {
3556 err = chip->info->ops->port_disable_learn_limit(chip, port);
3561 if (chip->info->ops->port_disable_pri_override) {
3562 err = chip->info->ops->port_disable_pri_override(chip, port);
3567 if (chip->info->ops->port_tag_remap) {
3568 err = chip->info->ops->port_tag_remap(chip, port);
3573 if (chip->info->ops->port_egress_rate_limiting) {
3574 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3579 if (chip->info->ops->port_setup_message_port) {
3580 err = chip->info->ops->port_setup_message_port(chip, port);
3585 if (chip->info->ops->serdes_set_tx_amplitude) {
3593 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3606 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3610 err = mv88e6xxx_port_vlan_map(chip, port);
3617 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3622 struct mv88e6xxx_chip *chip = ds->priv;
3624 if (chip->info->ops->port_set_jumbo_size)
3626 else if (chip->info->ops->set_max_frame_size)
3633 struct mv88e6xxx_chip *chip = ds->priv;
3639 if (!chip->info->ops->port_set_jumbo_size &&
3640 !chip->info->ops->set_max_frame_size) {
3650 mv88e6xxx_reg_lock(chip);
3651 if (chip->info->ops->port_set_jumbo_size)
3652 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3653 else if (chip->info->ops->set_max_frame_size &&
3655 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3656 mv88e6xxx_reg_unlock(chip);
3664 struct mv88e6xxx_chip *chip = ds->priv;
3667 mv88e6xxx_reg_lock(chip);
3668 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3669 mv88e6xxx_reg_unlock(chip);
3674 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3679 if (chip->info->ops->stats_set_histogram) {
3680 err = chip->info->ops->stats_set_histogram(chip);
3685 return mv88e6xxx_g1_stats_clear(chip);
3688 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip)
3696 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000);
3700 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy);
3704 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3710 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3711 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3713 dev_err(chip->dev,
3728 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3733 if (mv88e6390_setup_errata_applied(chip))
3737 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3738 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3743 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3744 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3749 return mv88e6xxx_software_reset(chip);
3762 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3767 if (!chip->info->ops->phy_read)
3770 mv88e6xxx_reg_lock(chip);
3771 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3772 mv88e6xxx_reg_unlock(chip);
3776 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3777 prod_id = family_prod_id_table[chip->info->family];
3789 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3793 if (!chip->info->ops->phy_read_c45)
3796 mv88e6xxx_reg_lock(chip);
3797 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3798 mv88e6xxx_reg_unlock(chip);
3806 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3809 if (!chip->info->ops->phy_write)
3812 mv88e6xxx_reg_lock(chip);
3813 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3814 mv88e6xxx_reg_unlock(chip);
3823 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3826 if (!chip->info->ops->phy_write_c45)
3829 mv88e6xxx_reg_lock(chip);
3830 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3831 mv88e6xxx_reg_unlock(chip);
3836 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3846 mv88e6xxx_reg_lock(chip);
3847 if (chip->info->family == MV88E6XXX_FAMILY_6393)
3848 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
3850 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
3851 mv88e6xxx_reg_unlock(chip);
3863 mdio_bus->chip = chip;
3879 bus->parent = chip->dev;
3880 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3881 mv88e6xxx_num_ports(chip) - 1,
3882 chip->info->phy_base_addr);
3885 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3892 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3893 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3898 list_add_tail(&mdio_bus->list, &chip->mdios);
3900 list_add(&mdio_bus->list, &chip->mdios);
3909 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3915 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3919 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3926 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3928 struct device_node *np = chip->dev->of_node;
3937 err = mv88e6xxx_mdio_register(chip, child, false);
3949 err = mv88e6xxx_mdio_register(chip, child, true);
3951 mv88e6xxx_mdios_unregister(chip);
3963 struct mv88e6xxx_chip *chip = ds->priv;
3968 mv88e6xxx_mdios_unregister(chip);
3973 struct mv88e6xxx_chip *chip = ds->priv;
3978 err = mv88e6xxx_mdios_register(chip);
3982 chip->ds = ds;
3983 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3990 if (mv88e6xxx_has_pvt(chip))
3994 mv88e6xxx_reg_lock(chip);
3996 if (chip->info->ops->setup_errata) {
3997 err = chip->info->ops->setup_errata(chip);
4003 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
4004 if (chip->info->ops->port_get_cmode) {
4005 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
4009 chip->ports[i].cmode = cmode;
4013 err = mv88e6xxx_vtu_setup(chip);
4020 err = mv88e6xxx_stu_setup(chip);
4025 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
4030 if (mv88e6xxx_is_invalid_port(chip, i)) {
4031 dev_err(chip->dev, "port %d is invalid\n", i);
4036 err = mv88e6xxx_setup_port(chip, i);
4041 err = mv88e6xxx_irl_setup(chip);
4045 err = mv88e6xxx_mac_setup(chip);
4049 err = mv88e6xxx_phy_setup(chip);
4053 err = mv88e6xxx_pvt_setup(chip);
4057 err = mv88e6xxx_atu_setup(chip);
4061 err = mv88e6xxx_broadcast_setup(chip, 0);
4065 err = mv88e6xxx_pot_setup(chip);
4069 err = mv88e6xxx_rmu_setup(chip);
4073 err = mv88e6xxx_rsvd2cpu_setup(chip);
4077 err = mv88e6xxx_trunk_setup(chip);
4081 err = mv88e6xxx_devmap_setup(chip);
4085 err = mv88e6xxx_pri_setup(chip);
4090 if (chip->info->ptp_support) {
4091 err = mv88e6xxx_ptp_setup(chip);
4095 err = mv88e6xxx_hwtstamp_setup(chip);
4100 err = mv88e6xxx_stats_setup(chip);
4105 mv88e6xxx_reg_unlock(chip);
4134 mv88e6xxx_mdios_unregister(chip);
4141 struct mv88e6xxx_chip *chip = ds->priv;
4144 if (chip->info->ops->pcs_ops &&
4145 chip->info->ops->pcs_ops->pcs_init) {
4146 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4156 struct mv88e6xxx_chip *chip = ds->priv;
4160 if (chip->info->ops->pcs_ops &&
4161 chip->info->ops->pcs_ops->pcs_teardown)
4162 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4167 struct mv88e6xxx_chip *chip = ds->priv;
4169 return chip->eeprom_len;
4175 struct mv88e6xxx_chip *chip = ds->priv;
4178 if (!chip->info->ops->get_eeprom)
4181 mv88e6xxx_reg_lock(chip);
4182 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4183 mv88e6xxx_reg_unlock(chip);
4196 struct mv88e6xxx_chip *chip = ds->priv;
4199 if (!chip->info->ops->set_eeprom)
4205 mv88e6xxx_reg_lock(chip);
4206 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4207 mv88e6xxx_reg_unlock(chip);
6542 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6549 mv88e6xxx_reg_lock(chip);
6550 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6551 mv88e6xxx_reg_unlock(chip);
6563 chip->info = info;
6565 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6566 chip->info->prod_num, chip->info->name, rev);
6571 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6576 /* dual_chip takes precedence over single/multi-chip modes */
6577 if (chip->info->dual_chip)
6581 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6582 * configured in single chip addressing mode. Setup the smi access as
6583 * single chip addressing mode and attempt to detect the model of the
6584 * switch, if this fails the device is not configured in single chip
6590 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6594 return mv88e6xxx_detect(chip);
6599 struct mv88e6xxx_chip *chip;
6601 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6602 if (!chip)
6605 chip->dev = dev;
6607 mutex_init(&chip->reg_lock);
6608 INIT_LIST_HEAD(&chip->mdios);
6609 idr_init(&chip->policies);
6610 INIT_LIST_HEAD(&chip->msts);
6612 return chip;
6619 struct mv88e6xxx_chip *chip = ds->priv;
6621 return chip->tag_protocol;
6627 struct mv88e6xxx_chip *chip = ds->priv;
6634 switch (chip->info->edsa_support) {
6638 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6650 old_protocol = chip->tag_protocol;
6651 chip->tag_protocol = proto;
6653 mv88e6xxx_reg_lock(chip);
6655 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6657 mv88e6xxx_reg_unlock(chip);
6661 mv88e6xxx_reg_unlock(chip);
6666 chip->tag_protocol = old_protocol;
6668 mv88e6xxx_reg_lock(chip);
6670 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6671 mv88e6xxx_reg_unlock(chip);
6680 struct mv88e6xxx_chip *chip = ds->priv;
6683 mv88e6xxx_reg_lock(chip);
6684 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6689 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid))
6693 mv88e6xxx_reg_unlock(chip);
6702 struct mv88e6xxx_chip *chip = ds->priv;
6705 mv88e6xxx_reg_lock(chip);
6706 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6707 mv88e6xxx_reg_unlock(chip);
6720 struct mv88e6xxx_chip *chip = ds->priv;
6725 mutex_lock(&chip->reg_lock);
6726 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6728 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6730 chip->ports[i].mirror_ingress :
6731 chip->ports[i].mirror_egress;
6739 err = mv88e6xxx_set_egress_port(chip, direction,
6745 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6747 mutex_unlock(&chip->reg_lock);
6758 struct mv88e6xxx_chip *chip = ds->priv;
6762 mutex_lock(&chip->reg_lock);
6763 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6766 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6768 chip->ports[i].mirror_ingress :
6769 chip->ports[i].mirror_egress;
6773 if (mv88e6xxx_set_egress_port(chip, direction,
6778 mutex_unlock(&chip->reg_lock);
6785 struct mv88e6xxx_chip *chip = ds->priv;
6792 ops = chip->info->ops;
6807 struct mv88e6xxx_chip *chip = ds->priv;
6810 mv88e6xxx_reg_lock(chip);
6816 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6824 err = chip->info->ops->port_set_ucast_flood(chip, port,
6833 err = chip->info->ops->port_set_mcast_flood(chip, port,
6842 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6850 mv88e6xxx_port_set_mab(chip, port, mab);
6856 err = mv88e6xxx_port_set_lock(chip, port, locked);
6861 mv88e6xxx_reg_unlock(chip);
6871 struct mv88e6xxx_chip *chip = ds->priv;
6875 if (!mv88e6xxx_has_lag(chip)) {
6911 struct mv88e6xxx_chip *chip = ds->priv;
6921 * port if the LAG port is on a remote chip.
6926 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6966 struct mv88e6xxx_chip *chip = ds->priv;
6975 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
7019 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
7042 struct mv88e6xxx_chip *chip = ds->priv;
7045 mv88e6xxx_reg_lock(chip);
7047 mv88e6xxx_reg_unlock(chip);
7056 struct mv88e6xxx_chip *chip = ds->priv;
7065 mv88e6xxx_reg_lock(chip);
7067 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
7075 mv88e6xxx_reg_unlock(chip);
7079 mv88e6xxx_port_set_trunk(chip, port, false, 0);
7081 mv88e6xxx_reg_unlock(chip);
7088 struct mv88e6xxx_chip *chip = ds->priv;
7091 mv88e6xxx_reg_lock(chip);
7093 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
7094 mv88e6xxx_reg_unlock(chip);
7101 struct mv88e6xxx_chip *chip = ds->priv;
7104 mv88e6xxx_reg_lock(chip);
7106 mv88e6xxx_reg_unlock(chip);
7115 struct mv88e6xxx_chip *chip = ds->priv;
7121 mv88e6xxx_reg_lock(chip);
7127 err = mv88e6xxx_pvt_map(chip, sw_index, port);
7130 mv88e6xxx_reg_unlock(chip);
7137 struct mv88e6xxx_chip *chip = ds->priv;
7140 mv88e6xxx_reg_lock(chip);
7142 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
7143 mv88e6xxx_reg_unlock(chip);
7218 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7220 struct device *dev = chip->dev;
7228 ds->num_ports = mv88e6xxx_num_ports(chip);
7229 ds->priv = chip;
7233 ds->ageing_time_min = chip->info->age_time_coeff;
7234 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7240 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7247 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7249 dsa_unregister_switch(chip->ds);
7286 struct mv88e6xxx_chip *chip;
7315 chip = mv88e6xxx_alloc_chip(dev);
7316 if (!chip) {
7321 chip->info = compat_info;
7323 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7324 if (IS_ERR(chip->reset)) {
7325 err = PTR_ERR(chip->reset);
7328 if (chip->reset)
7331 /* Detect if the device is configured in single chip addressing mode,
7334 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7336 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7340 err = mv88e6xxx_detect(chip);
7345 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7346 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7348 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7350 mv88e6xxx_phy_init(chip);
7352 if (chip->info->ops->get_eeprom) {
7355 &chip->eeprom_len);
7357 chip->eeprom_len = pdata->eeprom_len;
7360 mv88e6xxx_reg_lock(chip);
7361 err = mv88e6xxx_switch_reset(chip);
7362 mv88e6xxx_reg_unlock(chip);
7367 chip->irq = of_irq_get(np, 0);
7368 if (chip->irq == -EPROBE_DEFER) {
7369 err = chip->irq;
7375 chip->irq = pdata->irq;
7381 mv88e6xxx_reg_lock(chip);
7382 if (chip->irq > 0)
7383 err = mv88e6xxx_g1_irq_setup(chip);
7385 err = mv88e6xxx_irq_poll_setup(chip);
7386 mv88e6xxx_reg_unlock(chip);
7391 if (chip->info->g2_irqs > 0) {
7392 err = mv88e6xxx_g2_irq_setup(chip);
7397 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7401 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7405 err = mv88e6xxx_register_switch(chip);
7412 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7414 mv88e6xxx_g1_atu_prob_irq_free(chip);
7416 if (chip->info->g2_irqs > 0)
7417 mv88e6xxx_g2_irq_free(chip);
7419 if (chip->irq > 0)
7420 mv88e6xxx_g1_irq_free(chip);
7422 mv88e6xxx_irq_poll_free(chip);
7424 mv88e6xxx_phy_destroy(chip);
7435 struct mv88e6xxx_chip *chip;
7440 chip = ds->priv;
7442 if (chip->info->ptp_support) {
7443 mv88e6xxx_hwtstamp_free(chip);
7444 mv88e6xxx_ptp_free(chip);
7447 mv88e6xxx_unregister_switch(chip);
7449 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7450 mv88e6xxx_g1_atu_prob_irq_free(chip);
7452 if (chip->info->g2_irqs > 0)
7453 mv88e6xxx_g2_irq_free(chip);
7455 if (chip->irq > 0)
7456 mv88e6xxx_g1_irq_free(chip);
7458 mv88e6xxx_irq_poll_free(chip);
7460 mv88e6xxx_phy_destroy(chip);