Lines Matching full:nfc
214 static void pl35x_smc_update_regs(struct pl35x_nandc *nfc)
218 nfc->conf_regs + PL35X_SMC_DIRECT_CMD);
221 static int pl35x_smc_set_buswidth(struct pl35x_nandc *nfc, unsigned int bw)
226 writel(bw, nfc->conf_regs + PL35X_SMC_OPMODE);
227 pl35x_smc_update_regs(nfc);
232 static void pl35x_smc_clear_irq(struct pl35x_nandc *nfc)
235 nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);
238 static int pl35x_smc_wait_for_irq(struct pl35x_nandc *nfc)
243 ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_MEMC_STATUS, reg,
247 dev_err(nfc->dev,
251 pl35x_smc_clear_irq(nfc);
256 static int pl35x_smc_wait_for_ecc_done(struct pl35x_nandc *nfc)
261 ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_ECC_STATUS, reg,
265 dev_err(nfc->dev,
271 static int pl35x_smc_set_ecc_mode(struct pl35x_nandc *nfc,
278 ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);
281 writel(ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
289 return pl35x_smc_wait_for_ecc_done(nfc);
297 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
304 ret = pl35x_smc_set_buswidth(nfc, PL35X_SMC_OPMODE_BW_8);
306 ret = pl35x_smc_set_buswidth(nfc, PL35X_SMC_OPMODE_BW_16);
309 dev_err(nfc->dev, "Error in Buswidth\n");
315 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
318 if (chip == nfc->selected_chip)
322 writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);
323 pl35x_smc_update_regs(nfc);
326 writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
328 nfc->selected_chip = chip;
335 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
351 buf32[i] = readl(nfc->io_regs + data_phase_addr);
356 buf8[i] = readb(nfc->io_regs + PL35X_SMC_DATA_PHASE);
367 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
383 writel(buf32[i], nfc->io_regs + data_phase_addr);
388 writeb(buf8[i], nfc->io_regs + PL35X_SMC_DATA_PHASE);
394 static int pl35x_nand_correct_data(struct pl35x_nandc *nfc, unsigned char *buf,
448 static int pl35x_nand_read_eccbytes(struct pl35x_nandc *nfc,
456 ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));
466 static int pl35x_nand_recover_data_hwecc(struct pl35x_nandc *nfc,
479 ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));
490 stats = pl35x_nand_correct_data(nfc, data, read_ecc, calc_ecc);
506 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
516 ret = pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_APB);
534 writel(addr1, nfc->io_regs + cmd_addr);
536 writel(addr2, nfc->io_regs + cmd_addr);
541 ret = pl35x_smc_wait_for_ecc_done(nfc);
546 ret = pl35x_nand_read_eccbytes(nfc, chip, nfc->ecc_buf);
553 ret = mtd_ooblayout_set_eccbytes(mtd, nfc->ecc_buf, chip->oob_poi,
563 ret = pl35x_smc_wait_for_irq(nfc);
576 pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_BYPASS);
597 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
606 ret = pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_APB);
626 writel(addr1, nfc->io_regs + cmd_addr);
628 writel(addr2, nfc->io_regs + cmd_addr);
632 ret = pl35x_smc_wait_for_irq(nfc);
639 ret = pl35x_smc_wait_for_ecc_done(nfc);
646 ret = mtd_ooblayout_get_eccbytes(mtd, nfc->ecc_buf, chip->oob_poi, 0,
651 pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_BYPASS);
654 return pl35x_nand_recover_data_hwecc(nfc, chip, buf, nfc->ecc_buf);
657 pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_BYPASS);
665 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
722 writel(addr1, nfc->io_regs + cmd_addr);
724 writel(addr2, nfc->io_regs + cmd_addr);
739 ret = pl35x_smc_wait_for_irq(nfc);
787 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
798 mclk = of_clk_get_by_name(nfc->dev->parent->of_node, "memclk");
800 dev_err(nfc->dev, "Failed to retrieve SMC memclk\n");
805 * SDR timings are given in pico-seconds while NFC timings must be
868 static void pl35x_smc_set_ecc_pg_size(struct pl35x_nandc *nfc,
890 plnand->ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);
893 writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
896 static int pl35x_nand_init_hw_ecc_controller(struct pl35x_nandc *nfc,
903 dev_err(nfc->dev,
915 pl35x_smc_set_ecc_pg_size(nfc, chip, mtd->writesize);
917 nfc->ecc_buf = devm_kmalloc(nfc->dev, chip->ecc.bytes * chip->ecc.steps,
919 if (!nfc->ecc_buf)
932 dev_err(nfc->dev, "Unsupported OOB size\n");
943 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
954 dev_info(nfc->dev,
981 ret = pl35x_nand_init_hw_ecc_controller(nfc, chip);
986 dev_err(nfc->dev, "Unsupported ECC mode: %d\n",
1000 static int pl35x_nand_reset_state(struct pl35x_nandc *nfc)
1008 nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);
1011 ret = pl35x_smc_set_buswidth(nfc, PL35X_SMC_OPMODE_BW_8);
1016 ret = pl35x_smc_set_ecc_mode(nfc, NULL, PL35X_SMC_ECC_CFG_MODE_BYPASS);
1028 nfc->conf_regs + PL35X_SMC_ECC_CMD1);
1033 nfc->conf_regs + PL35X_SMC_ECC_CMD2);
1038 static int pl35x_nand_chip_init(struct pl35x_nandc *nfc,
1046 plnand = devm_kzalloc(nfc->dev, sizeof(*plnand), GFP_KERNEL);
1055 dev_err(nfc->dev, "Wrong CS %d\n", cs);
1059 if (test_and_set_bit(cs, &nfc->assigned_cs)) {
1060 dev_err(nfc->dev, "Already assigned CS %d\n", cs);
1069 chip->controller = &nfc->controller;
1071 mtd->dev.parent = nfc->dev;
1074 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1077 dev_err(nfc->dev, "Failed to allocate mtd->name\n");
1092 list_add_tail(&plnand->node, &nfc->chips);
1097 static void pl35x_nand_chips_cleanup(struct pl35x_nandc *nfc)
1103 list_for_each_entry_safe(plnand, tmp, &nfc->chips, node) {
1112 static int pl35x_nand_chips_init(struct pl35x_nandc *nfc)
1114 struct device_node *np = nfc->dev->of_node;
1119 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",
1125 ret = pl35x_nand_chip_init(nfc, nand_np);
1127 pl35x_nand_chips_cleanup(nfc);
1139 struct pl35x_nandc *nfc;
1142 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
1143 if (!nfc)
1146 nfc->dev = &pdev->dev;
1147 nand_controller_init(&nfc->controller);
1148 nfc->controller.ops = &pl35x_nandc_ops;
1149 INIT_LIST_HEAD(&nfc->chips);
1151 nfc->conf_regs = devm_ioremap_resource(&smc_amba->dev, &smc_amba->res);
1152 if (IS_ERR(nfc->conf_regs))
1153 return PTR_ERR(nfc->conf_regs);
1155 nfc->io_regs = devm_platform_ioremap_resource(pdev, 0);
1156 if (IS_ERR(nfc->io_regs))
1157 return PTR_ERR(nfc->io_regs);
1159 ret = pl35x_nand_reset_state(nfc);
1163 ret = pl35x_nand_chips_init(nfc);
1167 platform_set_drvdata(pdev, nfc);
1174 struct pl35x_nandc *nfc = platform_get_drvdata(pdev);
1176 pl35x_nand_chips_cleanup(nfc);