Lines Matching defs:host
24 #include <linux/mmc/host.h>
104 * @host: pointer to sdhci_host
115 static u32 esdhc_readl_fixup(struct sdhci_host *host,
118 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
162 * DTS properties of mmc host are used to enable each speed mode
176 static u16 esdhc_readw_fixup(struct sdhci_host *host,
179 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
200 static u8 esdhc_readb_fixup(struct sdhci_host *host,
227 * @host: pointer to sdhci_host
239 static u32 esdhc_writel_fixup(struct sdhci_host *host,
257 static u32 esdhc_writew_fixup(struct sdhci_host *host,
260 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
291 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
311 * If host control register is not standard, exit
314 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
333 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
339 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
341 value = ioread32be(host->ioaddr + reg);
343 ret = esdhc_readl_fixup(host, reg, value);
348 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
354 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
356 value = ioread32(host->ioaddr + reg);
358 ret = esdhc_readl_fixup(host, reg, value);
363 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
369 value = ioread32be(host->ioaddr + base);
370 ret = esdhc_readw_fixup(host, reg, value);
374 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
380 value = ioread32(host->ioaddr + base);
381 ret = esdhc_readw_fixup(host, reg, value);
385 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
391 value = ioread32be(host->ioaddr + base);
392 ret = esdhc_readb_fixup(host, reg, value);
396 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
402 value = ioread32(host->ioaddr + base);
403 ret = esdhc_readb_fixup(host, reg, value);
407 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
411 value = esdhc_writel_fixup(host, reg, val, 0);
412 iowrite32be(value, host->ioaddr + reg);
415 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
419 value = esdhc_writel_fixup(host, reg, val, 0);
420 iowrite32(value, host->ioaddr + reg);
423 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
425 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
431 value = ioread32be(host->ioaddr + base);
432 ret = esdhc_writew_fixup(host, reg, val, value);
434 iowrite32be(ret, host->ioaddr + base);
444 iowrite32be(ret, host->ioaddr + base);
449 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
451 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
457 value = ioread32(host->ioaddr + base);
458 ret = esdhc_writew_fixup(host, reg, val, value);
460 iowrite32(ret, host->ioaddr + base);
470 iowrite32(ret, host->ioaddr + base);
475 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
481 value = ioread32be(host->ioaddr + base);
482 ret = esdhc_writeb_fixup(host, reg, val, value);
483 iowrite32be(ret, host->ioaddr + base);
486 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
492 value = ioread32(host->ioaddr + base);
493 ret = esdhc_writeb_fixup(host, reg, val, value);
494 iowrite32(ret, host->ioaddr + base);
504 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
506 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
518 host->data->error = 0;
519 dmastart = sg_dma_address(host->data->sg);
520 dmanow = dmastart + host->data->bytes_xfered;
526 host->data->bytes_xfered = dmanow - dmastart;
527 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
530 static int esdhc_of_enable_dma(struct sdhci_host *host)
534 struct device *dev = mmc_dev(host->mmc);
543 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
550 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
554 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
556 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
565 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
567 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
578 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
580 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
595 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
602 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
612 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
616 mmc_hostname(host->mmc));
623 static void esdhc_flush_async_fifo(struct sdhci_host *host)
628 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
630 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
637 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
642 mmc_hostname(host->mmc));
649 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
651 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
659 host->mmc->actual_clock = 0;
660 esdhc_clock_enable(host, false);
669 if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
670 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
673 clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
679 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256)
682 while (host->max_clk / pre_div / div > clock_fixup && div < 16)
690 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
691 host->flags & SDHCI_HS400_TUNING)) {
703 mmc_hostname(host->mmc));
708 host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;
710 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
711 clock, host->mmc->actual_clock);
717 esdhc_clock_enable(host, false);
719 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
723 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
733 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
737 mmc_hostname(host->mmc));
744 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
746 temp = sdhci_readl(host, ESDHC_TBCTL);
747 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
748 temp = sdhci_readl(host, ESDHC_SDCLKCTL);
749 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
750 esdhc_clock_enable(host, true);
752 temp = sdhci_readl(host, ESDHC_DLLCFG0);
754 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
756 sdhci_writel(host, temp, ESDHC_DLLCFG0);
759 sdhci_writel(host, temp, ESDHC_DLLCFG0);
762 sdhci_writel(host, temp, ESDHC_DLLCFG0);
768 host, ESDHC_DLLSTAT0))
770 mmc_hostname(host->mmc));
772 temp = sdhci_readl(host, ESDHC_TBCTL);
773 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
775 esdhc_clock_enable(host, false);
776 esdhc_flush_async_fifo(host);
778 esdhc_clock_enable(host, true);
781 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
785 ctrl = sdhci_readl(host, ESDHC_PROCTL);
800 sdhci_writel(host, ctrl, ESDHC_PROCTL);
803 static void esdhc_reset(struct sdhci_host *host, u8 mask)
805 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
815 (host->flags & SDHCI_REQ_USE_DMA))
824 val = sdhci_readl(host, ESDHC_PROCTL);
828 sdhci_reset(host, mask);
836 val = sdhci_readl(host, ESDHC_PROCTL);
839 sdhci_writel(host, val, ESDHC_PROCTL);
841 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
842 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
851 val = sdhci_readl(host, ESDHC_TBCTL);
853 sdhci_writel(host, val, ESDHC_TBCTL);
860 val = sdhci_readl(host, ESDHC_DLLCFG1);
862 sdhci_writel(host, val, ESDHC_DLLCFG1);
888 struct sdhci_host *host = mmc_priv(mmc);
898 if (host->version < SDHCI_SPEC_300)
901 val = sdhci_readl(host, ESDHC_PROCTL);
906 sdhci_writel(host, val, ESDHC_PROCTL);
920 sdhci_writel(host, val, ESDHC_PROCTL);
930 sdhci_writel(host, val, ESDHC_PROCTL);
956 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
960 esdhc_clock_enable(host, false);
961 esdhc_flush_async_fifo(host);
963 val = sdhci_readl(host, ESDHC_TBCTL);
968 sdhci_writel(host, val, ESDHC_TBCTL);
970 esdhc_clock_enable(host, true);
973 static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start,
979 val = sdhci_readl(host, ESDHC_TBCTL);
982 sdhci_writel(host, val, ESDHC_TBCTL);
987 val = sdhci_readl(host, ESDHC_TBCTL);
988 sdhci_writel(host, val, ESDHC_TBCTL);
993 val = sdhci_readl(host, ESDHC_TBSTAT);
994 val = sdhci_readl(host, ESDHC_TBSTAT);
1000 static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start,
1003 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1013 esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr);
1016 sdhci_reset(host, SDHCI_RESET_DATA);
1018 sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS);
1038 struct sdhci_host *host = mmc_priv(mmc);
1039 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1048 sdhci_writel(host, val, ESDHC_TBPTR);
1051 val = sdhci_readl(host, ESDHC_TBCTL);
1054 sdhci_writel(host, val, ESDHC_TBCTL);
1064 struct sdhci_host *host = mmc_priv(mmc);
1065 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1077 if (host->clock > clk)
1078 esdhc_of_set_clock(host, clk);
1080 esdhc_tuning_block_enable(host, true);
1091 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
1093 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1098 esdhc_of_set_clock(host, host->clock);
1101 val = sdhci_readl(host, ESDHC_TBCTL);
1104 sdhci_writel(host, val, ESDHC_TBCTL);
1115 !host->tuning_err) {
1116 esdhc_tuning_window_ptr(host, &window_start,
1120 host->tuning_err = -EAGAIN;
1126 ret = host->tuning_err;
1132 host->flags |= SDHCI_HS400_TUNING;
1136 esdhc_prepare_sw_tuning(host, &window_start,
1145 ret = host->tuning_err;
1149 host->flags |= SDHCI_HS400_TUNING;
1151 clk = host->max_clk / (esdhc->div_ratio + 1);
1152 esdhc_of_set_clock(host, clk);
1164 esdhc_tuning_block_enable(host, false);
1166 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1168 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1174 static void esdhc_set_uhs_signaling(struct sdhci_host *host,
1184 val = sdhci_readl(host, ESDHC_TBCTL);
1186 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1188 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1190 val = sdhci_readl(host, ESDHC_SDCLKCTL);
1192 sdhci_writel(host, val, ESDHC_SDCLKCTL);
1194 esdhc_clock_enable(host, false);
1195 val = sdhci_readl(host, ESDHC_TBCTL);
1197 sdhci_writel(host, val, ESDHC_TBCTL);
1198 esdhc_clock_enable(host, true);
1200 val = sdhci_readl(host, ESDHC_DLLCFG0);
1202 sdhci_writel(host, val, ESDHC_DLLCFG0);
1204 val = sdhci_readl(host, ESDHC_TBCTL);
1206 sdhci_writel(host, val, ESDHC_TBCTL);
1208 esdhc_tuning_block_enable(host, false);
1212 esdhc_tuning_block_enable(host, true);
1214 sdhci_set_uhs_signaling(host, timing);
1217 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
1219 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1224 command = SDHCI_GET_CMD(sdhci_readw(host,
1227 sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
1230 sdhci_writel(host, SDHCI_INT_DATA_END,
1241 struct sdhci_host *host = dev_get_drvdata(dev);
1243 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
1245 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1246 mmc_retune_needed(host->mmc);
1248 return sdhci_suspend_host(host);
1253 struct sdhci_host *host = dev_get_drvdata(dev);
1254 int ret = sdhci_resume_host(host);
1258 esdhc_of_enable_dma(host);
1259 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
1342 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
1352 pltfm_host = sdhci_priv(host);
1355 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
1403 esdhc_clock_enable(host, false);
1404 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1414 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
1415 esdhc_clock_enable(host, true);
1426 struct sdhci_host *host;
1435 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
1438 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
1441 if (IS_ERR(host))
1442 return PTR_ERR(host);
1444 host->mmc_host_ops.start_signal_voltage_switch =
1446 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
1447 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
1448 host->tuning_delay = 1;
1450 esdhc_init(pdev, host);
1454 pltfm_host = sdhci_priv(host);
1467 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
1470 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1475 host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
1476 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1484 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1487 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1493 * host control register
1495 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
1500 ret = mmc_of_parse(host->mmc);
1504 mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1506 return sdhci_add_host(host);