mmc/host/owl-mmc.c

28 #define OWL_REG_SD_EN			0x0000
29 #define OWL_REG_SD_CTL			0x0004
30 #define OWL_REG_SD_STATE		0x0008
31 #define OWL_REG_SD_CMD			0x000c
32 #define OWL_REG_SD_ARG			0x0010
33 #define OWL_REG_SD_RSPBUF0		0x0014
34 #define OWL_REG_SD_RSPBUF1		0x0018
35 #define OWL_REG_SD_RSPBUF2		0x001c
36 #define OWL_REG_SD_RSPBUF3		0x0020
37 #define OWL_REG_SD_RSPBUF4		0x0024
38 #define OWL_REG_SD_DAT			0x0028
39 #define OWL_REG_SD_BLK_SIZE		0x002c
40 #define OWL_REG_SD_BLK_NUM		0x0030
41 #define OWL_REG_SD_BUF_SIZE		0x0034
45 #define OWL_SD_EN_RAN_SEED(x)		(((x) & 0x3f) << 24)
54 #define OWL_SD_EN_DATAWID(x)		(((x) & 0x3) << 0)
58 #define OWL_SD_CTL_TOUTCNT(x)		(((x) & 0x7f) << 24)
60 #define OWL_SD_CTL_RDELAY(x)		(((x) & 0xf) << 20)
61 #define OWL_SD_CTL_WDELAY(x)		(((x) & 0xf) << 16)
64 #define OWL_SD_CTL_TCN(x)		(((x) & 0xf) << 8)
68 #define OWL_SD_CTL_TM(x)		(((x) & 0xf) << 0)
70 #define OWL_SD_DELAY_LOW_CLK		0x0f
71 #define OWL_SD_DELAY_MID_CLK		0x0a
72 #define OWL_SD_DELAY_HIGH_CLK		0x09
73 #define OWL_SD_RDELAY_DDR50		0x0a
74 #define OWL_SD_WDELAY_DDR50		0x08
94 #define OWL_SD_STATE_CRC7ER		BIT(0)
179 	u32 cmd_rsp_mask = 0;
185 		mode = OWL_SD_CTL_TM(0);
223 	mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
231 		mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
274 			cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
276 			resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
278 			cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;
335 	data->error = 0;
337 	return 0;
349 		if (ret < 0) {
442 	reg &= ~0x03;
475 	mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
552 	return 0;
582 	owl_host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
631 	owl_host->irq = platform_get_irq(pdev, 0);
632 	if (owl_host->irq < 0) {
638 			       0, dev_name(&pdev->dev), owl_host);
653 	return 0;