Lines Matching defs:zq

301 	u32 zq = 0, val = 0;
304 	zq |= val << ZQ_REFINTERVAL_SHIFT;
307 	zq |= val << ZQ_ZQCL_MULT_SHIFT;
310 	zq |= val << ZQ_ZQINIT_MULT_SHIFT;
312 	zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
315 		zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
317 		zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
319 	zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
322 	zq |= val << ZQ_CS1EN_SHIFT;
324 	return zq;
706 	u32				pwr_mgmt_ctrl, zq, temp_alert_cfg;
725 	zq = get_zq_config_reg(addressing, device_info->cs1_used,
727 	writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);