Lines Matching refs:dev
46 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
48 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
52 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
57 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
62 void initGPIO(struct cx231xx *dev)
70 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
72 verve_read_byte(dev, 0x07, &val);
73 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
74 verve_write_byte(dev, 0x07, 0xF4);
75 verve_read_byte(dev, 0x07, &val);
76 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
78 cx231xx_capture_start(dev, 1, Vbi);
80 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
81 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
84 void uninitGPIO(struct cx231xx *dev)
88 cx231xx_capture_start(dev, 0, Vbi);
89 verve_write_byte(dev, 0x07, 0x14);
90 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
98 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
100 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
104 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
109 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
115 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
124 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
128 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
134 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
138 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
144 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
146 dev_dbg(dev->dev,
152 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
155 dev_dbg(dev->dev,
162 dev_dbg(dev->dev,
174 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
181 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
186 int cx231xx_afe_init_channels(struct cx231xx *dev)
191 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
192 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
193 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
196 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
199 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
200 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
201 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
204 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
205 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
206 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
215 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
216 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
217 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
220 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
222 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
224 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
228 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
229 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
230 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
235 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
240 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
242 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
256 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
265 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
269 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
273 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
277 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
283 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
287 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
293 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
304 cx231xx_Setup_AFE_for_LowIF(dev);
307 status = cx231xx_afe_setup_AFE_for_baseband(dev);
320 if ((mode != dev->afe_mode) &&
321 (dev->video_input == CX231XX_VMUX_TELEVISION))
322 status = cx231xx_afe_adjust_ref_count(dev,
325 dev->afe_mode = mode;
330 int cx231xx_afe_update_power_control(struct cx231xx *dev,
336 switch (dev->model) {
354 status = afe_write_byte(dev, SUP_BLK_PWRDN,
357 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
363 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
365 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
367 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
370 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
377 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
382 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
387 status = afe_write_byte(dev, SUP_BLK_PWRDN,
390 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
396 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
398 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
400 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
403 dev_dbg(dev->dev, "Invalid AV mode input\n");
411 status = afe_write_byte(dev, SUP_BLK_PWRDN,
414 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
420 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
422 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
424 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
427 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
434 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
439 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
444 status = afe_write_byte(dev, SUP_BLK_PWRDN,
447 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
453 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
455 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
457 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
460 dev_dbg(dev->dev, "Invalid AV mode input\n");
468 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
474 dev->video_input = video_input;
477 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
478 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
481 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
482 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
490 dev->afe_ref_count = 0x23C;
493 dev->afe_ref_count = 0x24C;
496 dev->afe_ref_count = 0x258;
499 dev->afe_ref_count = 0x260;
505 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
513 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
515 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
519 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
524 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
530 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
532 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
536 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
538 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
541 int cx231xx_check_fw(struct cx231xx *dev)
545 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
553 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
560 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
561 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
563 status = cx231xx_set_power_mode(dev,
566 dev_err(dev->dev,
572 status = cx231xx_set_decoder_video_input(dev,
578 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
579 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
581 status = cx231xx_set_power_mode(dev,
584 dev_err(dev->dev,
590 switch (dev->model) { /* i2c device tuners */
596 status = cx231xx_set_decoder_video_input(dev,
601 if (dev->tuner_type == TUNER_NXP_TDA18271)
602 status = cx231xx_set_decoder_video_input(dev,
606 status = cx231xx_set_decoder_video_input(dev,
614 dev_err(dev->dev, "%s: Unknown Input %d !\n",
620 dev->video_input = input;
625 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
631 if (pin_type != dev->video_input) {
632 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
634 dev_err(dev->dev,
642 status = cx231xx_afe_set_input_mux(dev, input);
644 dev_err(dev->dev,
652 status = vid_blk_read_word(dev, AFE_CTRL, &value);
660 status = vid_blk_write_word(dev, AFE_CTRL, value);
662 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
664 status = vid_blk_write_word(dev, OUT_CTRL1, value);
667 status = cx231xx_read_modify_write_i2c_dword(dev,
671 dev->board.output_mode);
674 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
676 dev_err(dev->dev,
683 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
692 status = vid_blk_write_word(dev, DFE_CTRL1, value);
695 status = cx231xx_read_modify_write_i2c_dword(dev,
701 status = cx231xx_read_modify_write_i2c_dword(dev,
709 status = vid_blk_read_word(dev, AFE_CTRL, &value);
716 status = vid_blk_write_word(dev, AFE_CTRL, value);
719 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
721 dev_err(dev->dev,
728 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
737 status = vid_blk_write_word(dev, DFE_CTRL1, value);
740 status = cx231xx_read_modify_write_i2c_dword(dev,
746 status = cx231xx_read_modify_write_i2c_dword(dev,
753 status = vid_blk_read_word(dev, AFE_CTRL, &value);
761 status = vid_blk_write_word(dev, AFE_CTRL, value);
763 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
769 if (dev->board.tuner_type == TUNER_XC5000) {
772 status = vid_blk_read_word(dev, AFE_CTRL, &value);
780 status = vid_blk_write_word(dev, AFE_CTRL, value);
782 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
784 status = vid_blk_write_word(dev, OUT_CTRL1, value);
787 status = cx231xx_read_modify_write_i2c_dword(dev,
790 dev->board.output_mode);
793 status = cx231xx_dif_set_standard(dev,
796 dev_err(dev->dev,
803 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
812 status = vid_blk_write_word(dev, DFE_CTRL1, value);
815 status = cx231xx_read_modify_write_i2c_dword(dev,
821 status = cx231xx_read_modify_write_i2c_dword(dev,
830 status = cx231xx_dif_set_standard(dev, dev->norm);
832 dev_err(dev->dev,
839 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
845 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
848 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
858 status = vid_blk_write_word(dev, DFE_CTRL1, value);
867 status = vid_blk_write_word(dev, DFE_CTRL1, value);
870 status = vid_blk_read_word(dev, PIN_CTRL, &value);
874 status = vid_blk_write_word(dev, PIN_CTRL, value);
877 status = cx231xx_read_modify_write_i2c_dword(dev,
880 dev->board.output_mode);
883 status = cx231xx_read_modify_write_i2c_dword(dev,
889 status = cx231xx_read_modify_write_i2c_dword(dev,
900 status = vid_blk_read_word(dev, AFE_CTRL, &value);
908 status = vid_blk_write_word(dev, AFE_CTRL, value);
910 if (dev->tuner_type == TUNER_NXP_TDA18271) {
911 status = vid_blk_read_word(dev, PIN_CTRL,
913 status = vid_blk_write_word(dev, PIN_CTRL,
924 status = cx231xx_read_modify_write_i2c_dword(dev,
929 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
932 status = vid_blk_write_word(dev, OUT_CTRL1, value);
938 void cx231xx_enable656(struct cx231xx *dev)
943 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
947 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
950 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
954 void cx231xx_disable656(struct cx231xx *dev)
958 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
960 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
963 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
972 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
976 dev_dbg(dev->dev, "%s: 0x%x\n",
977 __func__, (unsigned int)dev->norm);
980 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
982 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
983 dev_dbg(dev->dev, "%s: NTSC\n", __func__);
987 status = cx231xx_read_modify_write_i2c_dword(dev,
991 status = cx231xx_read_modify_write_i2c_dword(dev,
996 status = cx231xx_read_modify_write_i2c_dword(dev,
1002 status = cx231xx_read_modify_write_i2c_dword(dev,
1009 } else if (dev->norm & V4L2_STD_SECAM) {
1010 dev_dbg(dev->dev, "%s: SECAM\n", __func__);
1011 status = cx231xx_read_modify_write_i2c_dword(dev,
1015 status = cx231xx_read_modify_write_i2c_dword(dev,
1022 status = cx231xx_read_modify_write_i2c_dword(dev,
1030 status = cx231xx_read_modify_write_i2c_dword(dev,
1037 dev_dbg(dev->dev, "%s: PAL\n", __func__);
1038 status = cx231xx_read_modify_write_i2c_dword(dev,
1042 status = cx231xx_read_modify_write_i2c_dword(dev,
1049 status = cx231xx_read_modify_write_i2c_dword(dev,
1057 status = cx231xx_read_modify_write_i2c_dword(dev,
1069 int cx231xx_unmute_audio(struct cx231xx *dev)
1071 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1075 static int stopAudioFirmware(struct cx231xx *dev)
1077 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1080 static int restartAudioFirmware(struct cx231xx *dev)
1082 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1085 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1095 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1102 status = cx231xx_set_audio_decoder_input(dev, ainput);
1107 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1116 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1118 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1125 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1130 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1132 status = vid_blk_write_word(dev, AC97_CTL,
1136 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1143 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1144 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1147 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1148 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1152 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1153 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1159 status = stopAudioFirmware(dev);
1161 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1177 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1187 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1189 status = restartAudioFirmware(dev);
1191 switch (dev->board.tuner_type) {
1194 status = cx231xx_read_modify_write_i2c_dword(dev,
1202 status = cx231xx_read_modify_write_i2c_dword(dev,
1209 switch (dev->model) { /* i2c device tuners */
1221 dev_info(dev->dev,
1236 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1241 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1243 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1251 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1256 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1257 value |= (~dev->board.ctl_pin_status_mask);
1258 status = vid_blk_write_word(dev, PIN_CTRL, value);
1263 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1269 status = cx231xx_set_gpio_direction(dev,
1270 dev->board.
1274 status = cx231xx_set_gpio_value(dev,
1275 dev->board.agc_analog_digital_select_gpio,
1284 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
1291 * Should this code check dev->port_3_switch_enabled first
1293 * If yes, the flag dev->port_3_switch_enabled must be initialized
1297 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1313 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1318 dev->port_3_switch_enabled = is_port_3;
1325 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1331 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1332 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1333 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1335 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1336 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1337 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1342 static void cx231xx_dump_SC_reg(struct cx231xx *dev)
1345 dev_dbg(dev->dev, "%s!\n", __func__);
1347 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1349 dev_dbg(dev->dev,
1352 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1354 dev_dbg(dev->dev,
1357 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1359 dev_dbg(dev->dev,
1362 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1364 dev_dbg(dev->dev,
1368 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1370 dev_dbg(dev->dev,
1373 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1375 dev_dbg(dev->dev,
1378 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1380 dev_dbg(dev->dev,
1383 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1385 dev_dbg(dev->dev,
1389 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1391 dev_dbg(dev->dev,
1394 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1396 dev_dbg(dev->dev,
1399 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1401 dev_dbg(dev->dev,
1404 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1406 dev_dbg(dev->dev,
1410 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1412 dev_dbg(dev->dev,
1415 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1417 dev_dbg(dev->dev,
1420 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1422 dev_dbg(dev->dev,
1425 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1427 dev_dbg(dev->dev,
1431 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1433 dev_dbg(dev->dev,
1436 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1438 dev_dbg(dev->dev,
1444 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1449 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1451 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1453 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1455 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1467 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1469 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1471 afe_read_byte(dev, ADC_INPUT_CH3, &value);
1473 afe_write_byte(dev, ADC_INPUT_CH3, value);
1475 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1477 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1479 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1481 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1483 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1485 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1487 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1489 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1491 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1493 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1495 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1497 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1500 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1508 dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n");
1513 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1517 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1520 standard = dev->norm;
1521 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1528 dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n",
1532 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1554 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1562 dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1568 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1577 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1582 vid_blk_read_word(dev, DIF_MISC_CTRL,
1585 vid_blk_write_word(dev, DIF_MISC_CTRL,
1590 vid_blk_read_word(dev, DIF_MISC_CTRL,
1593 vid_blk_write_word(dev, DIF_MISC_CTRL,
1606 dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array));
1609 vid_blk_write_word(dev,
1618 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1627 status = cx231xx_reg_mask_write(dev,
1631 status = cx231xx_reg_mask_write(dev,
1635 status = cx231xx_reg_mask_write(dev,
1639 status = cx231xx_reg_mask_write(dev,
1645 status = cx231xx_reg_mask_write(dev,
1649 status = cx231xx_reg_mask_write(dev,
1654 status = cx231xx_reg_mask_write(dev,
1658 status = cx231xx_reg_mask_write(dev,
1662 status = cx231xx_reg_mask_write(dev,
1670 status = cx231xx_reg_mask_write(dev,
1674 status = cx231xx_reg_mask_write(dev,
1679 status = cx231xx_reg_mask_write(dev,
1683 status = cx231xx_reg_mask_write(dev,
1690 status = cx231xx_reg_mask_write(dev,
1694 status = cx231xx_reg_mask_write(dev,
1699 status = cx231xx_reg_mask_write(dev,
1703 status = cx231xx_reg_mask_write(dev,
1712 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1718 dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard);
1720 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1722 dev->norm = standard;
1724 switch (dev->model) {
1744 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1750 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1751 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1754 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1757 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1759 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1761 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1763 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1765 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1767 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1773 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1790 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1802 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1808 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1810 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1821 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1827 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1835 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1838 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1848 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1849 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1850 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1851 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1852 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1853 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1855 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1857 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1859 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1861 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1862 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1864 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1866 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1868 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1875 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1876 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1877 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1878 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1879 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1880 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1882 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1884 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1886 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1888 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1890 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1892 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1894 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1896 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1905 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1907 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1909 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1911 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1913 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1915 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1921 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1924 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1930 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1932 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1938 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1941 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1956 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1958 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1968 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1971 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1977 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1979 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1985 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1988 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2008 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2009 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2010 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2011 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2012 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2013 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2015 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2017 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2019 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2021 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2023 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2025 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2027 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2030 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2031 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2033 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2040 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2042 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2044 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2046 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2048 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2050 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2056 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2059 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2065 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2073 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2076 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2093 if (dev->active_mode == V4L2_TUNER_RADIO)
2097 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2102 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2108 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2112 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2117 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2121 dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n",
2122 __func__, dev->tuner_type);
2125 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2128 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2130 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2136 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2143 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2151 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2156 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2160 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2163 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2169 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2176 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2179 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2182 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2190 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2196 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2198 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2206 dev->ctl_ainput = audio_input;
2214 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2220 if (dev->power_mode != mode)
2221 dev->power_mode = mode;
2223 dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n",
2228 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2245 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2255 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2264 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2268 dev->xc_fw_load_done = 0;
2278 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2288 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2299 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2309 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2320 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2325 if (dev->board.tuner_type != TUNER_ABSENT) {
2327 if (dev->board.tuner_gpio)
2328 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2330 if (dev->cx231xx_reset_analog_tuner)
2331 dev->cx231xx_reset_analog_tuner(dev);
2343 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2353 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2363 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2374 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2384 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2389 if (dev->board.tuner_type != TUNER_ABSENT) {
2391 if (dev->board.tuner_gpio)
2392 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2394 if (dev->cx231xx_reset_analog_tuner)
2395 dev->cx231xx_reset_analog_tuner(dev);
2413 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2419 status = cx231xx_afe_update_power_control(dev, mode);
2422 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2424 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2433 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2439 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
2440 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2452 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2458 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2464 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
2466 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2477 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2483 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2489 if (dev->udev->speed == USB_SPEED_HIGH) {
2492 dev_dbg(dev->dev,
2495 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2499 dev_dbg(dev->dev,
2501 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2505 dev_dbg(dev->dev,
2508 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2512 dev_dbg(dev->dev,
2514 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2518 dev_dbg(dev->dev,
2521 if (dev->board.has_417) {
2522 dev_dbg(dev->dev,
2527 status = cx231xx_mode_register(dev,
2534 status = cx231xx_write_ctrl_reg(dev,
2542 status = cx231xx_write_ctrl_reg(dev,
2546 dev_dbg(dev->dev, "%s: BDA\n", __func__);
2547 status = cx231xx_mode_register(dev,
2549 status = cx231xx_mode_register(dev,
2555 dev_dbg(dev->dev,
2558 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2559 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2563 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2569 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2576 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2603 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2610 rc = cx231xx_start_stream(dev, ep_mask);
2614 rc = cx231xx_stop_stream(dev, ep_mask);
2624 static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val)
2629 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0);
2634 static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val)
2639 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1);
2656 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2668 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2670 value = dev->gpio_dir | (1 << pin_number);
2672 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val);
2675 dev->gpio_dir = value;
2691 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2701 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2703 value = dev->gpio_dir | (1 << pin_number);
2704 dev->gpio_dir = value;
2705 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2706 dev->gpio_val);
2710 value = dev->gpio_val & (~(1 << pin_number));
2712 value = dev->gpio_val | (1 << pin_number);
2715 dev->gpio_val = value;
2718 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2726 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2731 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2732 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2733 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2734 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2736 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2741 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2742 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2744 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2749 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2750 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2752 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2759 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2764 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2765 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2767 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2768 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2770 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2775 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2776 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2778 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2784 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2785 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2788 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2795 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2801 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2802 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2807 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2808 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2809 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2810 dev->gpio_val);
2813 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2814 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2815 dev->gpio_val);
2818 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2819 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2820 dev->gpio_val);
2823 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2824 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2825 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2826 dev->gpio_val);
2829 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2830 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2831 dev->gpio_val);
2834 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2835 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2836 dev->gpio_val);
2842 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2853 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2854 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2855 dev->gpio_val);
2858 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2859 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2860 dev->gpio_val);
2863 gpio_logic_value = dev->gpio_val;
2864 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2865 &dev->gpio_val);
2866 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2869 dev->gpio_val = gpio_logic_value;
2875 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2876 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2884 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2893 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2894 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2896 gpio_logic_value = dev->gpio_val;
2897 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2901 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2902 &dev->gpio_val);
2904 } while (((dev->gpio_val &
2905 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2909 dev_dbg(dev->dev,
2918 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val);
2920 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2921 dev->gpio_val = gpio_logic_value;
2922 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2925 dev->gpio_val = gpio_logic_value;
2926 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2931 dev->gpio_val = gpio_logic_value;
2932 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2933 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2934 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2939 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2944 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2945 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2948 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2949 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2950 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2953 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2954 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2957 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2958 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2961 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2962 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2967 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2972 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2973 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2974 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2977 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2978 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2981 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2982 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2993 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
2999 mutex_lock(&dev->gpio_i2c_lock);
3002 status = cx231xx_gpio_i2c_start(dev);
3005 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3008 status = cx231xx_gpio_i2c_read_ack(dev);
3014 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3018 status = cx231xx_gpio_i2c_write_ack(dev);
3023 status = cx231xx_gpio_i2c_write_nak(dev);
3026 status = cx231xx_gpio_i2c_end(dev);
3029 mutex_unlock(&dev->gpio_i2c_lock);
3037 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3042 mutex_lock(&dev->gpio_i2c_lock);
3045 cx231xx_gpio_i2c_start(dev);
3048 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3051 cx231xx_gpio_i2c_read_ack(dev);
3055 cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3058 cx231xx_gpio_i2c_read_ack(dev);
3062 cx231xx_gpio_i2c_end(dev);
3065 mutex_unlock(&dev->gpio_i2c_lock);