media/rc/ene_ir.c

35 static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
37 	outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
38 	outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
42 static u8 ene_read_reg(struct ene_device *dev, u16 reg)
45 	ene_set_reg_addr(dev, reg);
46 	retval = inb(dev->hw_io + ENE_IO);
52 static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
55 	ene_set_reg_addr(dev, reg);
56 	outb(value, dev->hw_io + ENE_IO);
60 static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
63 	ene_set_reg_addr(dev, reg);
64 	outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
68 static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
71 	ene_set_reg_addr(dev, reg);
72 	outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
76 static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
80 		ene_set_reg_mask(dev, reg, mask);
82 		ene_clear_reg_mask(dev, reg, mask);
86 static int ene_hw_detect(struct ene_device *dev)
92 	ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
93 	chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
94 	chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
95 	ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
97 	hw_revision = ene_read_reg(dev, ENE_ECHV);
98 	old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
100 	dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
101 		(ene_read_reg(dev, ENE_PLLFRL) >> 4);
104 		dev->rx_period_adjust =
105 			dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
117 	pr_notice("PLL freq = %d\n", dev->pll_freq);
125 		dev->hw_revision = ENE_HW_C;
128 		dev->hw_revision = ENE_HW_B;
131 		dev->hw_revision = ENE_HW_D;
136 	if (dev->hw_revision < ENE_HW_C)
139 	fw_reg1 = ene_read_reg(dev, ENE_FW1);
140 	fw_reg2 = ene_read_reg(dev, ENE_FW2);
144 	dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A);
145 	dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING);
146 	dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF);
148 	if (dev->hw_learning_and_tx_capable)
149 		dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT);
153 	if (dev->hw_learning_and_tx_capable) {
162 			  dev->hw_use_gpio_0a ? "40" : "0A");
164 		if (dev->hw_fan_input)
168 	if (!dev->hw_fan_input)
170 			  dev->hw_use_gpio_0a ? "0A" : "40");
172 	if (dev->hw_extra_buffer)
178 static void ene_rx_setup_hw_buffer(struct ene_device *dev)
182 	ene_rx_read_hw_pointer(dev);
183 	dev->r_pointer = dev->w_pointer;
185 	if (!dev->hw_extra_buffer) {
186 		dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
190 	tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
191 	tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
192 	dev->extra_buf1_address = tmp;
194 	dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
196 	tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
197 	tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
198 	dev->extra_buf2_address = tmp;
200 	dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
202 	dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
206 		  dev->extra_buf1_address, dev->extra_buf1_len);
208 		  dev->extra_buf2_address, dev->extra_buf2_len);
210 	pr_notice("Total buffer len = %d\n", dev->buffer_len);
212 	if (dev->buffer_len > 64 || dev->buffer_len < 16)
215 	if (dev->extra_buf1_address > 0xFBFC ||
216 					dev->extra_buf1_address < 0xEC00)
219 	if (dev->extra_buf2_address > 0xFBFC ||
220 					dev->extra_buf2_address < 0xEC00)
223 	if (dev->r_pointer > dev->buffer_len)
226 	ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
230 	dev->hw_extra_buffer = false;
231 	ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
236 static void ene_rx_restore_hw_buffer(struct ene_device *dev)
238 	if (!dev->hw_extra_buffer)
241 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
242 				dev->extra_buf1_address & 0xFF);
243 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
244 				dev->extra_buf1_address >> 8);
245 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
247 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
248 				dev->extra_buf2_address & 0xFF);
249 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
250 				dev->extra_buf2_address >> 8);
251 	ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
252 				dev->extra_buf2_len);
253 	ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
257 static void ene_rx_read_hw_pointer(struct ene_device *dev)
259 	if (dev->hw_extra_buffer)
260 		dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
262 		dev->w_pointer = ene_read_reg(dev, ENE_FW2)
266 		dev->w_pointer, dev->r_pointer);
270 static int ene_rx_get_sample_reg(struct ene_device *dev)
274 	if (dev->r_pointer == dev->w_pointer) {
276 		ene_rx_read_hw_pointer(dev);
279 	if (dev->r_pointer == dev->w_pointer) {
280 		dbg_verbose("RB: end of data at %d", dev->r_pointer);
284 	dbg_verbose("RB: reading at offset %d", dev->r_pointer);
285 	r_pointer = dev->r_pointer;
287 	dev->r_pointer++;
288 	if (dev->r_pointer == dev->buffer_len)
289 		dev->r_pointer = 0;
291 	dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
300 	if (r_pointer < dev->extra_buf1_len) {
302 		return dev->extra_buf1_address + r_pointer;
305 	r_pointer -= dev->extra_buf1_len;
307 	if (r_pointer < dev->extra_buf2_len) {
309 		return dev->extra_buf2_address + r_pointer;
317 static void ene_rx_sense_carrier(struct ene_device *dev)
320 	int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
321 	int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
338 	if (dev->carrier_detect_enabled) {
344 		ir_raw_event_store(dev->rdev, &ev);
349 static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable)
351 	ene_set_clear_reg_mask(dev, ENE_CIRCFG,
356 static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a)
358 	ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
365 static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable)
367 	if (!dev->hw_fan_input)
371 		ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
373 		ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
374 		ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
379 static void ene_rx_setup(struct ene_device *dev)
381 	bool learning_mode = dev->learning_mode_enabled ||
382 					dev->carrier_detect_enabled;
389 	ene_write_reg(dev, ENE_CIRCFG2, 0x00);
394 			dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
396 	ene_write_reg(dev, ENE_CIRRLC_CFG,
400 	if (dev->hw_revision < ENE_HW_C)
405 		WARN_ON(!dev->hw_learning_and_tx_capable);
412 		ene_rx_select_input(dev, !dev->hw_use_gpio_0a);
413 		dev->rx_fan_input_inuse = false;
416 		ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
419 		ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
420 		ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
421 			dev->carrier_detect_enabled || debug);
423 		if (dev->hw_fan_input)
424 			dev->rx_fan_input_inuse = true;
426 			ene_rx_select_input(dev, dev->hw_use_gpio_0a);
429 		ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
430 		ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
434 	if (dev->rx_fan_input_inuse) {
435 		dev->rdev->rx_resolution = ENE_FW_SAMPLE_PERIOD_FAN;
439 		dev->rdev->min_timeout = dev->rdev->max_timeout =
443 		dev->rdev->rx_resolution = sample_period;
450 		dev->rdev->min_timeout = 127 * sample_period;
451 		dev->rdev->max_timeout = 200000;
454 	if (dev->rdev->timeout > dev->rdev->max_timeout)
455 		dev->rdev->timeout = dev->rdev->max_timeout;
456 	if (dev->rdev->timeout < dev->rdev->min_timeout)
457 		dev->rdev->timeout = dev->rdev->min_timeout;
461 static void ene_rx_enable_hw(struct ene_device *dev)
466 	if (dev->hw_revision < ENE_HW_C) {
467 		ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
468 		ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
470 		reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
473 		reg_value |= (dev->irq & ENE_IRQ_MASK);
474 		ene_write_reg(dev, ENE_IRQ, reg_value);
478 	ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse);
479 	ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse);
482 	ene_irq_status(dev);
485 	ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
488 	ir_raw_event_set_idle(dev->rdev, true);
492 static void ene_rx_enable(struct ene_device *dev)
494 	ene_rx_enable_hw(dev);
495 	dev->rx_enabled = true;
499 static void ene_rx_disable_hw(struct ene_device *dev)
502 	ene_rx_enable_cir_engine(dev, false);
503 	ene_rx_enable_fan_input(dev, false);
506 	ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
507 	ir_raw_event_set_idle(dev->rdev, true);
511 static void ene_rx_disable(struct ene_device *dev)
513 	ene_rx_disable_hw(dev);
514 	dev->rx_enabled = false;
520 static void ene_rx_reset(struct ene_device *dev)
522 	ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
523 	ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
527 static void ene_tx_set_carrier(struct ene_device *dev)
532 	spin_lock_irqsave(&dev->hw_lock, flags);
534 	ene_set_clear_reg_mask(dev, ENE_CIRCFG,
535 		ENE_CIRCFG_TX_CARR, dev->tx_period > 0);
537 	if (!dev->tx_period)
540 	BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0);
542 	tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
547 	dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
550 	ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
551 	ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
553 	spin_unlock_irqrestore(&dev->hw_lock, flags);
557 static void ene_tx_set_transmitters(struct ene_device *dev)
561 	spin_lock_irqsave(&dev->hw_lock, flags);
562 	ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
563 					!!(dev->transmitter_mask & 0x01));
564 	ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
565 					!!(dev->transmitter_mask & 0x02));
566 	spin_unlock_irqrestore(&dev->hw_lock, flags);
570 static void ene_tx_enable(struct ene_device *dev)
572 	u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
573 	u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
575 	dev->saved_conf1 = conf1;
588 	if (dev->hw_revision == ENE_HW_C)
593 	ene_write_reg(dev, ENE_CIRCFG, conf1);
597 static void ene_tx_disable(struct ene_device *dev)
599 	ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
600 	dev->tx_buffer = NULL;
604 /* TX one sample - must be called with dev->hw_lock*/
605 static void ene_tx_sample(struct ene_device *dev)
609 	bool pulse = dev->tx_sample_pulse;
611 	if (!dev->tx_buffer) {
617 	if (!dev->tx_sample) {
619 		if (dev->tx_pos == dev->tx_len) {
620 			if (!dev->tx_done) {
622 				dev->tx_done = true;
626 				ene_tx_disable(dev);
627 				complete(&dev->tx_complete);
632 		sample = dev->tx_buffer[dev->tx_pos++];
633 		dev->tx_sample_pulse = !dev->tx_sample_pulse;
635 		dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
637 		if (!dev->tx_sample)
638 			dev->tx_sample = 1;
641 	raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
642 	dev->tx_sample -= raw_tx;
649 	ene_write_reg(dev,
650 		dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
652 	dev->tx_reg = !dev->tx_reg;
656 		mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
662 	struct ene_device *dev = timer_container_of(dev, t, tx_sim_timer);
665 	spin_lock_irqsave(&dev->hw_lock, flags);
666 	ene_tx_sample(dev);
667 	spin_unlock_irqrestore(&dev->hw_lock, flags);
672 static int ene_irq_status(struct ene_device *dev)
678 	fw_flags2 = ene_read_reg(dev, ENE_FW2);
680 	if (dev->hw_revision < ENE_HW_C) {
681 		irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
686 		ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
690 	irq_status = ene_read_reg(dev, ENE_IRQ);
695 	ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
696 	ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
701 		ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
705 	fw_flags1 = ene_read_reg(dev, ENE_FW1);
707 		ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
722 	struct ene_device *dev = (struct ene_device *)data;
725 	spin_lock_irqsave(&dev->hw_lock, flags);
728 	ene_rx_read_hw_pointer(dev);
729 	irq_status = ene_irq_status(dev);
738 		if (!dev->hw_learning_and_tx_capable) {
742 		ene_tx_sample(dev);
750 	if (dev->hw_learning_and_tx_capable)
751 		ene_rx_sense_carrier(dev);
755 	if (!dev->hw_extra_buffer)
756 		dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
760 		reg = ene_rx_get_sample_reg(dev);
766 		hw_value = ene_read_reg(dev, reg);
768 		if (dev->rx_fan_input_inuse) {
773 			hw_value |= ene_read_reg(dev, reg + offset) << 8;
785 			if (dev->rx_period_adjust) {
787 				hw_sample /= (100 + dev->rx_period_adjust);
791 		if (!dev->hw_extra_buffer && !hw_sample) {
792 			dev->r_pointer = dev->w_pointer;
800 		ir_raw_event_store_with_filter(dev->rdev, &ev);
803 	ir_raw_event_handle(dev->rdev);
805 	spin_unlock_irqrestore(&dev->hw_lock, flags);
810 static void ene_setup_default_settings(struct ene_device *dev)
812 	dev->tx_period = 32;
813 	dev->tx_duty_cycle = 50; /*%*/
814 	dev->transmitter_mask = 0x03;
815 	dev->learning_mode_enabled = learning_mode_force;
818 	dev->rdev->timeout = MS_TO_US(150);
822 static void ene_setup_hw_settings(struct ene_device *dev)
824 	if (dev->hw_learning_and_tx_capable) {
825 		ene_tx_set_carrier(dev);
826 		ene_tx_set_transmitters(dev);
829 	ene_rx_setup(dev);
835 	struct ene_device *dev = rdev->priv;
838 	spin_lock_irqsave(&dev->hw_lock, flags);
839 	ene_rx_enable(dev);
840 	spin_unlock_irqrestore(&dev->hw_lock, flags);
847 	struct ene_device *dev = rdev->priv;
849 	spin_lock_irqsave(&dev->hw_lock, flags);
851 	ene_rx_disable(dev);
852 	spin_unlock_irqrestore(&dev->hw_lock, flags);
858 	struct ene_device *dev = rdev->priv;
868 	dev->transmitter_mask = tx_mask;
869 	ene_tx_set_transmitters(dev);
876 	struct ene_device *dev = rdev->priv;
892 	dev->tx_period = period;
893 	ene_tx_set_carrier(dev);
900 	struct ene_device *dev = rdev->priv;
902 	dev->tx_duty_cycle = duty_cycle;
903 	ene_tx_set_carrier(dev);
910 	struct ene_device *dev = rdev->priv;
912 	if (enable == dev->learning_mode_enabled)
915 	spin_lock_irqsave(&dev->hw_lock, flags);
916 	dev->learning_mode_enabled = enable;
917 	ene_rx_disable(dev);
918 	ene_rx_setup(dev);
919 	ene_rx_enable(dev);
920 	spin_unlock_irqrestore(&dev->hw_lock, flags);
926 	struct ene_device *dev = rdev->priv;
929 	if (enable == dev->carrier_detect_enabled)
932 	spin_lock_irqsave(&dev->hw_lock, flags);
933 	dev->carrier_detect_enabled = enable;
934 	ene_rx_disable(dev);
935 	ene_rx_setup(dev);
936 	ene_rx_enable(dev);
937 	spin_unlock_irqrestore(&dev->hw_lock, flags);
944 	struct ene_device *dev = rdev->priv;
947 		ene_rx_reset(dev);
955 	struct ene_device *dev = rdev->priv;
958 	dev->tx_buffer = buf;
959 	dev->tx_len = n;
960 	dev->tx_pos = 0;
961 	dev->tx_reg = 0;
962 	dev->tx_done = 0;
963 	dev->tx_sample = 0;
964 	dev->tx_sample_pulse = false;
966 	dbg("TX: %d samples", dev->tx_len);
968 	spin_lock_irqsave(&dev->hw_lock, flags);
970 	ene_tx_enable(dev);
973 	ene_tx_sample(dev);
974 	ene_tx_sample(dev);
976 	spin_unlock_irqrestore(&dev->hw_lock, flags);
978 	if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
980 		spin_lock_irqsave(&dev->hw_lock, flags);
981 		ene_tx_disable(dev);
982 		spin_unlock_irqrestore(&dev->hw_lock, flags);
993 	struct ene_device *dev;
996 	dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
998 	if (!dev || !rdev)
1005 	dev->hw_io = -1;
1006 	dev->irq = -1;
1015 	spin_lock_init(&dev->hw_lock);
1017 	dev->hw_io = pnp_port_start(pnp_dev, 0);
1018 	dev->irq = pnp_irq(pnp_dev, 0);
1021 	pnp_set_drvdata(pnp_dev, dev);
1022 	dev->pnp_dev = pnp_dev;
1029 	error = ene_hw_detect(dev);
1033 	if (!dev->hw_learning_and_tx_capable && txsim) {
1034 		dev->hw_learning_and_tx_capable = true;
1035 		timer_setup(&dev->tx_sim_timer, ene_tx_irqsim, 0);
1039 	if (!dev->hw_learning_and_tx_capable)
1043 	rdev->priv = dev;
1051 	if (dev->hw_learning_and_tx_capable) {
1053 		init_completion(&dev->tx_complete);
1062 	dev->rdev = rdev;
1064 	ene_rx_setup_hw_buffer(dev);
1065 	ene_setup_default_settings(dev);
1066 	ene_setup_hw_settings(dev);
1068 	device_set_wakeup_capable(&pnp_dev->dev, true);
1069 	device_set_wakeup_enable(&pnp_dev->dev, true);
1077 	if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
1081 	if (request_irq(dev->irq, ene_isr,
1082 			IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
1090 	release_region(dev->hw_io, ENE_IO_SIZE);
1096 	kfree(dev);
1103 	struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1106 	rc_unregister_device(dev->rdev);
1107 	timer_delete_sync(&dev->tx_sim_timer);
1108 	spin_lock_irqsave(&dev->hw_lock, flags);
1109 	ene_rx_disable(dev);
1110 	ene_rx_restore_hw_buffer(dev);
1111 	spin_unlock_irqrestore(&dev->hw_lock, flags);
1113 	free_irq(dev->irq, dev);
1114 	release_region(dev->hw_io, ENE_IO_SIZE);
1115 	kfree(dev);
1119 static void ene_enable_wake(struct ene_device *dev, bool enable)
1122 	ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
1128 	struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1129 	bool wake = device_may_wakeup(&dev->pnp_dev->dev);
1131 	if (!wake && dev->rx_enabled)
1132 		ene_rx_disable_hw(dev);
1134 	ene_enable_wake(dev, wake);
1140 	struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1141 	ene_setup_hw_settings(dev);
1143 	if (dev->rx_enabled)
1144 		ene_rx_enable(dev);
1146 	ene_enable_wake(dev, false);
1153 	struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1154 	ene_enable_wake(dev, true);