samsung/exynos4-is/fimc-lite-reg.c

23 	u32 cfg;
25 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
26 	cfg |= FLITE_REG_CIGCTRL_SWRST_REQ;
27 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
30 		cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
31 		if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY)
36 	cfg |= FLITE_REG_CIGCTRL_SWRST;
37 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
42 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);
43 	cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM;
44 	writel(cfg, dev->regs + FLITE_REG_CISTATUS);
56 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);
57 	cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND;
58 	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);
63 	u32 cfg, intsrc;
77 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
78 	cfg |= FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK;
79 	cfg &= ~intsrc;
80 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
85 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
86 	cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN;
87 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
92 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
93 	cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN;
94 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
103 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
105 		cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
107 		cfg &= ~FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
108 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
131 	u32 cfg;
144 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
145 	cfg &= ~FLITE_REG_CIGCTRL_FMT_MASK;
146 	cfg |= src_pixfmt_map[i][2];
147 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
149 	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);
150 	cfg &= ~(FLITE_REG_CISRCSIZE_ORDER422_MASK |
152 	cfg |= (f->f_width << 16) | f->f_height;
153 	cfg |= src_pixfmt_map[i][1];
154 	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);
161 	u32 cfg;
163 	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);
164 	cfg &= ~FLITE_REG_CIWDOFST_OFST_MASK;
165 	cfg |= (f->rect.left << 16) | f->rect.top;
166 	cfg |= FLITE_REG_CIWDOFST_WINOFSEN;
167 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);
172 	cfg = (hoff2 << 16) | voff2;
173 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);
179 	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);
181 		cfg &= ~FLITE_REG_CIGENERAL_CAM_B;
183 		cfg |= FLITE_REG_CIGENERAL_CAM_B;
184 	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);
191 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
195 		cfg &= ~(FLITE_REG_CIGCTRL_SELCAM_MIPI |
201 			cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK;
204 			cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC;
207 			cfg |= FLITE_REG_CIGCTRL_INVPOLHREF;
209 		cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI;
212 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
219 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);
221 	cfg &= ~FLITE_REG_CIODMAFMT_PACK12;
224 		cfg |= FLITE_REG_CIODMAFMT_PACK12;
226 	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);
238 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);
244 	cfg &= ~FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK;
245 	writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);
250 	u32 cfg;
253 	cfg = readl(dev->regs + FLITE_REG_CIOCAN);
254 	cfg &= ~FLITE_REG_CIOCAN_MASK;
255 	cfg |= (f->f_height << 16) | f->f_width;
256 	writel(cfg, dev->regs + FLITE_REG_CIOCAN);
259 	cfg = readl(dev->regs + FLITE_REG_CIOOFF);
260 	cfg &= ~FLITE_REG_CIOOFF_MASK;
261 	cfg |= (f->rect.top << 16) | f->rect.left;
262 	writel(cfg, dev->regs + FLITE_REG_CIOOFF);
268 	u32 cfg;
280 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);
281 	cfg |= BIT(index);
282 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
287 	u32 cfg;
292 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);
293 	cfg &= ~BIT(index);
294 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
301 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
304 		cfg |= FLITE_REG_CIGCTRL_ODMA_DISABLE;
305 		writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
309 	cfg &= ~FLITE_REG_CIGCTRL_ODMA_DISABLE;
310 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
343 		u32 cfg = readl(dev->regs + registers[i].offset);
345 			  registers[i].name, cfg);