samsung/exynos-gsc/gsc-regs.c

22 	u32 cfg;
25 		cfg = readl(dev->regs + GSC_SW_RESET);
26 		if (!cfg)
36 	u32 cfg;
38 	cfg = readl(dev->regs + GSC_IRQ);
40 		cfg |= GSC_IRQ_FRMDONE_MASK;
42 		cfg &= ~GSC_IRQ_FRMDONE_MASK;
43 	writel(cfg, dev->regs + GSC_IRQ);
48 	u32 cfg;
50 	cfg = readl(dev->regs + GSC_IRQ);
52 		cfg |= GSC_IRQ_ENABLE;
54 		cfg &= ~GSC_IRQ_ENABLE;
55 	writel(cfg, dev->regs + GSC_IRQ);
61 	u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
64 	cfg &= ~mask;
65 	cfg |= enable << shift;
67 	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
68 	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK);
69 	writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK);
75 	u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
78 	cfg &= ~mask;
79 	cfg |= enable << shift;
81 	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
82 	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK);
83 	writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK);
111 	u32 cfg = readl(dev->regs + GSC_IN_CON);
112 	cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
115 		cfg |= GSC_IN_PATH_MEMORY;
117 	writel(cfg, dev->regs + GSC_IN_CON);
124 	u32 cfg;
127 	cfg = GSC_SRCIMG_OFFSET_X(frame->crop.left);
128 	cfg |= GSC_SRCIMG_OFFSET_Y(frame->crop.top);
129 	writel(cfg, dev->regs + GSC_SRCIMG_OFFSET);
132 	cfg = GSC_SRCIMG_WIDTH(frame->f_width);
133 	cfg |= GSC_SRCIMG_HEIGHT(frame->f_height);
134 	writel(cfg, dev->regs + GSC_SRCIMG_SIZE);
137 	cfg = GSC_CROPPED_WIDTH(frame->crop.width);
138 	cfg |= GSC_CROPPED_HEIGHT(frame->crop.height);
139 	writel(cfg, dev->regs + GSC_CROPPED_SIZE);
146 	u32 cfg;
148 	cfg = readl(dev->regs + GSC_IN_CON);
150 		cfg |= GSC_IN_RGB_HD_WIDE;
152 		cfg |= GSC_IN_RGB_SD_WIDE;
155 		cfg |= GSC_IN_RGB565;
157 		cfg |= GSC_IN_XRGB8888;
159 	writel(cfg, dev->regs + GSC_IN_CON);
167 	u32 cfg;
169 	cfg = readl(dev->regs + GSC_IN_CON);
170 	cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
173 	writel(cfg, dev->regs + GSC_IN_CON);
184 		cfg |= GSC_IN_YUV422_1P;
186 			cfg |= GSC_IN_YUV422_1P_ORDER_LSB_Y;
188 			cfg |= GSC_IN_YUV422_1P_OEDER_LSB_C;
190 			cfg |= GSC_IN_CHROMA_ORDER_CBCR;
192 			cfg |= GSC_IN_CHROMA_ORDER_CRCB;
196 			cfg |= GSC_IN_YUV420_2P;
198 			cfg |= GSC_IN_YUV422_2P;
200 			cfg |= GSC_IN_CHROMA_ORDER_CBCR;
202 			cfg |= GSC_IN_CHROMA_ORDER_CRCB;
206 			cfg |= GSC_IN_YUV420_3P;
208 			cfg |= GSC_IN_YUV422_3P;
213 		cfg |= GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE;
215 	writel(cfg, dev->regs + GSC_IN_CON);
222 	u32 cfg = readl(dev->regs + GSC_OUT_CON);
223 	cfg &= ~GSC_OUT_PATH_MASK;
226 		cfg |= GSC_OUT_PATH_MEMORY;
228 		cfg |= GSC_OUT_PATH_LOCAL;
230 	writel(cfg, dev->regs + GSC_OUT_CON);
237 	u32 cfg;
241 		cfg = GSC_DSTIMG_OFFSET_X(frame->crop.left);
242 		cfg |= GSC_DSTIMG_OFFSET_Y(frame->crop.top);
243 		writel(cfg, dev->regs + GSC_DSTIMG_OFFSET);
245 		cfg = GSC_DSTIMG_WIDTH(frame->f_width);
246 		cfg |= GSC_DSTIMG_HEIGHT(frame->f_height);
247 		writel(cfg, dev->regs + GSC_DSTIMG_SIZE);
253 		cfg = GSC_SCALED_WIDTH(frame->crop.height);
254 		cfg |= GSC_SCALED_HEIGHT(frame->crop.width);
256 		cfg = GSC_SCALED_WIDTH(frame->crop.width);
257 		cfg |= GSC_SCALED_HEIGHT(frame->crop.height);
259 	writel(cfg, dev->regs + GSC_SCALED_SIZE);
266 	u32 cfg;
268 	cfg = readl(dev->regs + GSC_OUT_CON);
270 		cfg |= GSC_OUT_RGB_HD_WIDE;
272 		cfg |= GSC_OUT_RGB_SD_WIDE;
275 		cfg |= GSC_OUT_RGB565;
277 		cfg |= GSC_OUT_XRGB8888;
279 	writel(cfg, dev->regs + GSC_OUT_CON);
287 	u32 cfg;
289 	cfg = readl(dev->regs + GSC_OUT_CON);
290 	cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
293 	writel(cfg, dev->regs + GSC_OUT_CON);
301 		cfg |= GSC_OUT_YUV444;
310 		cfg |= GSC_OUT_YUV422_1P;
312 			cfg |= GSC_OUT_YUV422_1P_ORDER_LSB_Y;
314 			cfg |= GSC_OUT_YUV422_1P_OEDER_LSB_C;
316 			cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
318 			cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
322 			cfg |= GSC_OUT_YUV420_2P;
324 			cfg |= GSC_OUT_YUV422_2P;
326 			cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
328 			cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
331 		cfg |= GSC_OUT_YUV420_3P;
336 		cfg |= GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE;
339 	writel(cfg, dev->regs + GSC_OUT_CON);
346 	u32 cfg;
348 	cfg = GSC_PRESC_SHFACTOR(sc->pre_shfactor);
349 	cfg |= GSC_PRESC_H_RATIO(sc->pre_hratio);
350 	cfg |= GSC_PRESC_V_RATIO(sc->pre_vratio);
351 	writel(cfg, dev->regs + GSC_PRE_SCALE_RATIO);
358 	u32 cfg;
360 	cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
361 	writel(cfg, dev->regs + GSC_MAIN_H_RATIO);
363 	cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
364 	writel(cfg, dev->regs + GSC_MAIN_V_RATIO);
370 	u32 cfg;
372 	cfg = readl(dev->regs + GSC_IN_CON);
373 	cfg &= ~GSC_IN_ROT_MASK;
377 		cfg |= GSC_IN_ROT_270;
380 		cfg |= GSC_IN_ROT_180;
384 			cfg |= GSC_IN_ROT_90_XFLIP;
386 			cfg |= GSC_IN_ROT_90_YFLIP;
388 			cfg |= GSC_IN_ROT_90;
392 			cfg |= GSC_IN_ROT_XFLIP;
394 			cfg |= GSC_IN_ROT_YFLIP;
397 	writel(cfg, dev->regs + GSC_IN_CON);
404 	u32 cfg;
411 	cfg = readl(dev->regs + GSC_OUT_CON);
412 	cfg &= ~GSC_OUT_GLOBAL_ALPHA_MASK;
414 	cfg |= GSC_OUT_GLOBAL_ALPHA(ctx->gsc_ctrls.global_alpha->val);
415 	writel(cfg, dev->regs + GSC_OUT_CON);
421 	u32 cfg;
423 	cfg = readl(dev->regs + GSC_ENABLE);
424 	cfg |= GSC_ENABLE_SFR_UPDATE;
425 	writel(cfg, dev->regs + GSC_ENABLE);