3  * Driver for Renesas R-Car VIN
19 #include "rcar-vin.h"
25 /* Register offsets for R-Car VIN */
82 /* Register bit fields for R-Car VIN */
167 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset)  in rvin_write()  argument
169 	iowrite32(value, vin->base + offset);  in rvin_write()
172 static u32 rvin_read(struct rvin_dev *vin, u32 offset)  in rvin_read()  argument
174 	return ioread32(vin->base + offset);  in rvin_read()
181 static bool rvin_scaler_needed(const struct rvin_dev *vin)  in rvin_scaler_needed()  argument
183 	return !(vin->crop.width == vin->format.width &&  in rvin_scaler_needed()
184 		 vin->compose.width == vin->format.width &&  in rvin_scaler_needed()
185 		 vin->crop.height == vin->format.height &&  in rvin_scaler_needed()
186 		 vin->compose.height == vin->format.height);  in rvin_scaler_needed()
507 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)  in rvin_set_coeff()  argument
528 	rvin_write(vin, p_set->coeff_set[0], VNC1A_REG);  in rvin_set_coeff()
529 	rvin_write(vin, p_set->coeff_set[1], VNC1B_REG);  in rvin_set_coeff()
530 	rvin_write(vin, p_set->coeff_set[2], VNC1C_REG);  in rvin_set_coeff()
532 	rvin_write(vin, p_set->coeff_set[3], VNC2A_REG);  in rvin_set_coeff()
533 	rvin_write(vin, p_set->coeff_set[4], VNC2B_REG);  in rvin_set_coeff()
534 	rvin_write(vin, p_set->coeff_set[5], VNC2C_REG);  in rvin_set_coeff()
536 	rvin_write(vin, p_set->coeff_set[6], VNC3A_REG);  in rvin_set_coeff()
537 	rvin_write(vin, p_set->coeff_set[7], VNC3B_REG);  in rvin_set_coeff()
538 	rvin_write(vin, p_set->coeff_set[8], VNC3C_REG);  in rvin_set_coeff()
540 	rvin_write(vin, p_set->coeff_set[9], VNC4A_REG);  in rvin_set_coeff()
541 	rvin_write(vin, p_set->coeff_set[10], VNC4B_REG);  in rvin_set_coeff()
542 	rvin_write(vin, p_set->coeff_set[11], VNC4C_REG);  in rvin_set_coeff()
544 	rvin_write(vin, p_set->coeff_set[12], VNC5A_REG);  in rvin_set_coeff()
545 	rvin_write(vin, p_set->coeff_set[13], VNC5B_REG);  in rvin_set_coeff()
546 	rvin_write(vin, p_set->coeff_set[14], VNC5C_REG);  in rvin_set_coeff()
548 	rvin_write(vin, p_set->coeff_set[15], VNC6A_REG);  in rvin_set_coeff()
549 	rvin_write(vin, p_set->coeff_set[16], VNC6B_REG);  in rvin_set_coeff()
550 	rvin_write(vin, p_set->coeff_set[17], VNC6C_REG);  in rvin_set_coeff()
552 	rvin_write(vin, p_set->coeff_set[18], VNC7A_REG);  in rvin_set_coeff()
553 	rvin_write(vin, p_set->coeff_set[19], VNC7B_REG);  in rvin_set_coeff()
554 	rvin_write(vin, p_set->coeff_set[20], VNC7C_REG);  in rvin_set_coeff()
556 	rvin_write(vin, p_set->coeff_set[21], VNC8A_REG);  in rvin_set_coeff()
557 	rvin_write(vin, p_set->coeff_set[22], VNC8B_REG);  in rvin_set_coeff()
558 	rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);  in rvin_set_coeff()
561 void rvin_scaler_gen2(struct rvin_dev *vin)  in rvin_scaler_gen2()  argument
567 	if (vin->crop.height != vin->compose.height)  in rvin_scaler_gen2()
568 		ys = (4096 * vin->crop.height) / vin->compose.height;  in rvin_scaler_gen2()
569 	rvin_write(vin, ys, VNYS_REG);  in rvin_scaler_gen2()
572 	if (vin->crop.width != vin->compose.width)  in rvin_scaler_gen2()
573 		xs = (4096 * vin->crop.width) / vin->compose.width;  in rvin_scaler_gen2()
579 	rvin_write(vin, xs, VNXS_REG);  in rvin_scaler_gen2()
585 	rvin_set_coeff(vin, xs);  in rvin_scaler_gen2()
588 	rvin_write(vin, 0, VNSPPOC_REG);  in rvin_scaler_gen2()
589 	rvin_write(vin, 0, VNSLPOC_REG);  in rvin_scaler_gen2()
590 	rvin_write(vin, vin->format.width - 1, VNEPPOC_REG);  in rvin_scaler_gen2()
592 	if (V4L2_FIELD_HAS_BOTH(vin->format.field))  in rvin_scaler_gen2()
593 		rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG);  in rvin_scaler_gen2()
595 		rvin_write(vin, vin->format.height - 1, VNELPOC_REG);  in rvin_scaler_gen2()
597 	vin_dbg(vin,  in rvin_scaler_gen2()
599 		vin->crop.width, vin->crop.height, vin->crop.left,  in rvin_scaler_gen2()
600 		vin->crop.top, ys, xs, vin->format.width, vin->format.height,  in rvin_scaler_gen2()
620 void rvin_scaler_gen3(struct rvin_dev *vin)  in rvin_scaler_gen3()  argument
626 	vnmc = rvin_read(vin, VNMC_REG);  in rvin_scaler_gen3()
629 	if (!rvin_scaler_needed(vin)) {  in rvin_scaler_gen3()
630 		rvin_write(vin, vnmc & ~VNMC_SCLE, VNMC_REG);  in rvin_scaler_gen3()
634 	ratio_h = rvin_uds_scale_ratio(vin->crop.width, vin->compose.width);  in rvin_scaler_gen3()
637 	ratio_v = rvin_uds_scale_ratio(vin->crop.height, vin->compose.height);  in rvin_scaler_gen3()
640 	clip_size = vin->compose.width << 16;  in rvin_scaler_gen3()
642 	switch (vin->format.field) {  in rvin_scaler_gen3()
646 		clip_size |= vin->compose.height / 2;  in rvin_scaler_gen3()
649 		clip_size |= vin->compose.height;  in rvin_scaler_gen3()
653 	rvin_write(vin, vnmc | VNMC_SCLE, VNMC_REG);  in rvin_scaler_gen3()
654 	rvin_write(vin, VNUDS_CTRL_AMD, VNUDS_CTRL_REG);  in rvin_scaler_gen3()
655 	rvin_write(vin, (ratio_h << 16) | ratio_v, VNUDS_SCALE_REG);  in rvin_scaler_gen3()
656 	rvin_write(vin, (bwidth_h << 16) | bwidth_v, VNUDS_PASS_BWIDTH_REG);  in rvin_scaler_gen3()
657 	rvin_write(vin, clip_size, VNUDS_CLIP_SIZE_REG);  in rvin_scaler_gen3()
659 	vin_dbg(vin, "Pre-Clip: %ux%u@%u:%u Post-Clip: %ux%u@%u:%u\n",  in rvin_scaler_gen3()
660 		vin->crop.width, vin->crop.height, vin->crop.left,  in rvin_scaler_gen3()
661 		vin->crop.top, vin->compose.width, vin->compose.height,  in rvin_scaler_gen3()
662 		vin->compose.left, vin->compose.top);  in rvin_scaler_gen3()
665 void rvin_crop_scale_comp(struct rvin_dev *vin)  in rvin_crop_scale_comp()  argument
671 	rvin_write(vin, vin->crop.left, VNSPPRC_REG);  in rvin_crop_scale_comp()
672 	rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);  in rvin_crop_scale_comp()
673 	rvin_write(vin, vin->crop.top, VNSLPRC_REG);  in rvin_crop_scale_comp()
674 	rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG);  in rvin_crop_scale_comp()
676 	if (vin->scaler)  in rvin_crop_scale_comp()
677 		vin->scaler(vin);  in rvin_crop_scale_comp()
679 	fmt = rvin_format_from_pixel(vin, vin->format.pixelformat);  in rvin_crop_scale_comp()
680 	stride = vin->format.bytesperline / fmt->bpp;  in rvin_crop_scale_comp()
681 	rvin_write(vin, stride, VNIS_REG);  in rvin_crop_scale_comp()
688 static int rvin_setup(struct rvin_dev *vin)  in rvin_setup()  argument
693 	switch (vin->format.field) {  in rvin_setup()
723 	switch (vin->mbus_code) {  in rvin_setup()
725 		if (vin->is_csi)  in rvin_setup()
734 		if (vin->is_csi)  in rvin_setup()
745 		if (!vin->is_csi &&  in rvin_setup()
746 		    vin->parallel.mbus_type == V4L2_MBUS_BT656)  in rvin_setup()
758 		if (!vin->is_csi &&  in rvin_setup()
759 		    vin->parallel.mbus_type == V4L2_MBUS_BT656)  in rvin_setup()
772 		if (vin->info->model == RCAR_GEN4)  in rvin_setup()
786 	if (vin->info->model == RCAR_GEN3 || vin->info->model == RCAR_GEN4)  in rvin_setup()
791 	if (!vin->is_csi) {  in rvin_setup()
793 		if (!(vin->parallel.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))  in rvin_setup()
797 		if (!(vin->parallel.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))  in rvin_setup()
801 		if (vin->parallel.bus.flags & V4L2_MBUS_DATA_ENABLE_LOW)  in rvin_setup()
804 		switch (vin->mbus_code) {  in rvin_setup()
806 			if (vin->parallel.bus.bus_width == 8 &&  in rvin_setup()
807 			    vin->parallel.bus.data_shift == 8)  in rvin_setup()
818 	switch (vin->format.pixelformat) {  in rvin_setup()
821 		rvin_write(vin,  in rvin_setup()
822 			   ALIGN(vin->format.bytesperline * vin->format.height,  in rvin_setup()
824 		dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ?  in rvin_setup()
847 		dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB;  in rvin_setup()
850 		dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB;  in rvin_setup()
873 		vin_err(vin, "Invalid pixelformat (0x%x)\n",  in rvin_setup()
874 			vin->format.pixelformat);  in rvin_setup()
881 	if (!vin->info->use_isp) {  in rvin_setup()
886 		if (vin->info->model == RCAR_GEN3 || vin->info->model == RCAR_GEN4) {  in rvin_setup()
888 			if (vin->is_csi)  in rvin_setup()
901 	rvin_write(vin, interrupts, VNINTS_REG);  in rvin_setup()
903 	rvin_write(vin, interrupts, VNIE_REG);  in rvin_setup()
905 	rvin_write(vin, dmr, VNDMR_REG);  in rvin_setup()
906 	rvin_write(vin, dmr2, VNDMR2_REG);  in rvin_setup()
909 	rvin_write(vin, vnmc | VNMC_ME, VNMC_REG);  in rvin_setup()
914 static bool rvin_capture_active(struct rvin_dev *vin)  in rvin_capture_active()  argument
916 	return rvin_read(vin, VNMS_REG) & VNMS_CA;  in rvin_capture_active()
919 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms)  in rvin_get_active_field()  argument
921 	if (vin->format.field == V4L2_FIELD_ALTERNATE) {  in rvin_get_active_field()
928 	return vin->format.field;  in rvin_get_active_field()
931 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)  in rvin_set_slot_addr()  argument
937 	fmt = rvin_format_from_pixel(vin, vin->format.pixelformat);  in rvin_set_slot_addr()
943 	offsetx = vin->compose.left * fmt->bpp;  in rvin_set_slot_addr()
944 	offsety = vin->compose.top * vin->format.bytesperline;  in rvin_set_slot_addr()
954 	rvin_write(vin, offset, VNMB_REG(slot));  in rvin_set_slot_addr()
963 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)  in rvin_fill_hw_slot()  argument
970 	if (WARN_ON(vin->buf_hw[slot].buffer))  in rvin_fill_hw_slot()
973 	if (list_empty(&vin->buf_list)) {  in rvin_fill_hw_slot()
974 		vin->buf_hw[slot].buffer = NULL;  in rvin_fill_hw_slot()
975 		phys_addr = vin->scratch_phys;  in rvin_fill_hw_slot()
978 		buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);  in rvin_fill_hw_slot()
981 		vin->buf_hw[slot].buffer = vbuf;  in rvin_fill_hw_slot()
987 	vin_dbg(vin, "Filling HW slot: %d buffer: %p\n",  in rvin_fill_hw_slot()
988 		slot, vin->buf_hw[slot].buffer);  in rvin_fill_hw_slot()
990 	vin->buf_hw[slot].phys = phys_addr;  in rvin_fill_hw_slot()
991 	rvin_set_slot_addr(vin, slot, phys_addr);  in rvin_fill_hw_slot()
994 static int rvin_capture_start(struct rvin_dev *vin)  in rvin_capture_start()  argument
999 		vin->buf_hw[slot].buffer = NULL;  in rvin_capture_start()
1000 		rvin_fill_hw_slot(vin, slot);  in rvin_capture_start()
1003 	ret = rvin_setup(vin);  in rvin_capture_start()
1007 	rvin_crop_scale_comp(vin);  in rvin_capture_start()
1009 	vin_dbg(vin, "Starting to capture\n");  in rvin_capture_start()
1012 	rvin_write(vin, VNFC_C_FRAME, VNFC_REG);  in rvin_capture_start()
1017 static void rvin_capture_stop(struct rvin_dev *vin)  in rvin_capture_stop()  argument
1020 	rvin_write(vin, 0, VNFC_REG);  in rvin_capture_stop()
1023 	rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG);  in rvin_capture_stop()
1035 	struct rvin_dev *vin = data;  in rvin_irq()  local
1041 	spin_lock_irqsave(&vin->qlock, flags);  in rvin_irq()
1043 	status = rvin_read(vin, VNINTS_REG);  in rvin_irq()
1047 	rvin_write(vin, status, VNINTS_REG);  in rvin_irq()
1054 			.u.frame_sync.frame_sequence = vin->sequence,  in rvin_irq()
1057 		v4l2_event_queue(&vin->vdev, &event);  in rvin_irq()
1061 	capture = vin->format.field == V4L2_FIELD_NONE ||  in rvin_irq()
1062 		vin->format.field == V4L2_FIELD_ALTERNATE ?  in rvin_irq()
1068 	if (!vin->running) {  in rvin_irq()
1069 		vin_dbg(vin, "IRQ while not running, ignoring\n");  in rvin_irq()
1074 	vnms = rvin_read(vin, VNMS_REG);  in rvin_irq()
1081 	if (!vin->sequence) {  in rvin_irq()
1083 			vin_dbg(vin, "Starting sync slot: %d\n", slot);  in rvin_irq()
1087 		vin_dbg(vin, "Capture start synced!\n");  in rvin_irq()
1091 	if (vin->buf_hw[slot].buffer) {  in rvin_irq()
1092 		vin->buf_hw[slot].buffer->field =  in rvin_irq()
1093 			rvin_get_active_field(vin, vnms);  in rvin_irq()
1094 		vin->buf_hw[slot].buffer->sequence = vin->sequence;  in rvin_irq()
1095 		vin->buf_hw[slot].buffer->vb2_buf.timestamp = ktime_get_ns();  in rvin_irq()
1096 		vb2_buffer_done(&vin->buf_hw[slot].buffer->vb2_buf,  in rvin_irq()
1098 		vin->buf_hw[slot].buffer = NULL;  in rvin_irq()
1101 		vin_dbg(vin, "Dropping frame %u\n", vin->sequence);  in rvin_irq()
1104 	vin->sequence++;  in rvin_irq()
1107 	rvin_fill_hw_slot(vin, slot);  in rvin_irq()
1109 	spin_unlock_irqrestore(&vin->qlock, flags);  in rvin_irq()
1114 static void return_unused_buffers(struct rvin_dev *vin,  in return_unused_buffers()  argument
1120 	spin_lock_irqsave(&vin->qlock, flags);  in return_unused_buffers()
1122 	list_for_each_entry_safe(buf, node, &vin->buf_list, list) {  in return_unused_buffers()
1127 	spin_unlock_irqrestore(&vin->qlock, flags);  in return_unused_buffers()
1135 	struct rvin_dev *vin = vb2_get_drv_priv(vq);  in rvin_queue_setup()  local
1139 		return sizes[0] < vin->format.sizeimage ? -EINVAL : 0;  in rvin_queue_setup()
1142 	sizes[0] = vin->format.sizeimage;  in rvin_queue_setup()
1149 	struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);  in rvin_buffer_prepare()  local
1150 	unsigned long size = vin->format.sizeimage;  in rvin_buffer_prepare()
1153 		vin_err(vin, "buffer too small (%lu < %lu)\n",  in rvin_buffer_prepare()
1166 	struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);  in rvin_buffer_queue()  local
1169 	spin_lock_irqsave(&vin->qlock, flags);  in rvin_buffer_queue()
1171 	list_add_tail(to_buf_list(vbuf), &vin->buf_list);  in rvin_buffer_queue()
1173 	spin_unlock_irqrestore(&vin->qlock, flags);  in rvin_buffer_queue()
1176 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd,  in rvin_mc_validate_format()  argument
1195 		if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR8)  in rvin_mc_validate_format()
1199 		if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG8)  in rvin_mc_validate_format()
1203 		if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG8)  in rvin_mc_validate_format()
1207 		if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB8)  in rvin_mc_validate_format()
1211 		if (vin->format.pixelformat != V4L2_PIX_FMT_GREY)  in rvin_mc_validate_format()
1215 		if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR10)  in rvin_mc_validate_format()
1219 		if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG10)  in rvin_mc_validate_format()
1223 		if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG10)  in rvin_mc_validate_format()
1227 		if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB10)  in rvin_mc_validate_format()
1233 	vin->mbus_code = fmt.format.code;  in rvin_mc_validate_format()
1245 		switch (vin->format.field) {  in rvin_mc_validate_format()
1254 			/* Use VIN hardware to combine the two fields */  in rvin_mc_validate_format()
1265 	if (rvin_scaler_needed(vin)) {  in rvin_mc_validate_format()
1267 		if ((vin->info->model == RCAR_GEN3 || vin->info->model == RCAR_GEN4) &&  in rvin_mc_validate_format()
1268 		    vin->format.pixelformat == V4L2_PIX_FMT_NV12)  in rvin_mc_validate_format()
1271 		if (!vin->scaler)  in rvin_mc_validate_format()
1274 		if (vin->format.pixelformat == V4L2_PIX_FMT_NV12) {  in rvin_mc_validate_format()
1275 			if (ALIGN(fmt.format.width, 32) != vin->format.width ||  in rvin_mc_validate_format()
1276 			    ALIGN(fmt.format.height, 32) != vin->format.height)  in rvin_mc_validate_format()
1279 			if (fmt.format.width != vin->format.width ||  in rvin_mc_validate_format()
1280 			    fmt.format.height != vin->format.height)  in rvin_mc_validate_format()
1285 	if (fmt.format.code != vin->mbus_code)  in rvin_mc_validate_format()
1291 static int rvin_set_stream(struct rvin_dev *vin, int on)  in rvin_set_stream()  argument
1297 	pad = media_pad_remote_pad_first(&vin->pad);  in rvin_set_stream()
1304 		video_device_pipeline_stop(&vin->vdev);  in rvin_set_stream()
1308 	ret = rvin_mc_validate_format(vin, sd, pad);  in rvin_set_stream()
1312 	ret = video_device_pipeline_alloc_start(&vin->vdev);  in rvin_set_stream()
1320 		video_device_pipeline_stop(&vin->vdev);  in rvin_set_stream()
1325 int rvin_start_streaming(struct rvin_dev *vin)  in rvin_start_streaming()  argument
1330 	ret = rvin_set_stream(vin, 1);  in rvin_start_streaming()
1334 	spin_lock_irqsave(&vin->qlock, flags);  in rvin_start_streaming()
1336 	vin->sequence = 0;  in rvin_start_streaming()
1338 	ret = rvin_capture_start(vin);  in rvin_start_streaming()
1340 		rvin_set_stream(vin, 0);  in rvin_start_streaming()
1342 	vin->running = true;  in rvin_start_streaming()
1344 	spin_unlock_irqrestore(&vin->qlock, flags);  in rvin_start_streaming()
1351 	struct rvin_dev *vin = vb2_get_drv_priv(vq);  in rvin_start_streaming_vq()  local
1355 	vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,  in rvin_start_streaming_vq()
1356 					  &vin->scratch_phys, GFP_KERNEL);  in rvin_start_streaming_vq()
1357 	if (!vin->scratch)  in rvin_start_streaming_vq()
1360 	ret = rvin_start_streaming(vin);  in rvin_start_streaming_vq()
1366 	dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,  in rvin_start_streaming_vq()
1367 			  vin->scratch_phys);  in rvin_start_streaming_vq()
1369 	return_unused_buffers(vin, VB2_BUF_STATE_QUEUED);  in rvin_start_streaming_vq()
1374 void rvin_stop_streaming(struct rvin_dev *vin)  in rvin_stop_streaming()  argument
1378 	spin_lock_irqsave(&vin->qlock, flags);  in rvin_stop_streaming()
1380 	if (!vin->running) {  in rvin_stop_streaming()
1381 		spin_unlock_irqrestore(&vin->qlock, flags);  in rvin_stop_streaming()
1387 		rvin_capture_stop(vin);  in rvin_stop_streaming()
1390 		if (!rvin_capture_active(vin)) {  in rvin_stop_streaming()
1394 		spin_unlock_irqrestore(&vin->qlock, flags);  in rvin_stop_streaming()
1396 		spin_lock_irqsave(&vin->qlock, flags);  in rvin_stop_streaming()
1399 	if (rvin_capture_active(vin))  in rvin_stop_streaming()
1400 		vin_err(vin, "Hardware did not stop\n");  in rvin_stop_streaming()
1402 	vin->running = false;  in rvin_stop_streaming()
1404 	spin_unlock_irqrestore(&vin->qlock, flags);  in rvin_stop_streaming()
1406 	rvin_set_stream(vin, 0);  in rvin_stop_streaming()
1409 	rvin_write(vin, 0, VNIE_REG);  in rvin_stop_streaming()
1413 		if (vin->buf_hw[i].buffer)  in rvin_stop_streaming()
1414 			vb2_buffer_done(&vin->buf_hw[i].buffer->vb2_buf,  in rvin_stop_streaming()
1422 	struct rvin_dev *vin = vb2_get_drv_priv(vq);  in rvin_stop_streaming_vq()  local
1424 	rvin_stop_streaming(vin);  in rvin_stop_streaming_vq()
1427 	dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,  in rvin_stop_streaming_vq()
1428 			  vin->scratch_phys);  in rvin_stop_streaming_vq()
1430 	return_unused_buffers(vin, VB2_BUF_STATE_ERROR);  in rvin_stop_streaming_vq()
1441 void rvin_dma_unregister(struct rvin_dev *vin)  in rvin_dma_unregister()  argument
1443 	mutex_destroy(&vin->lock);  in rvin_dma_unregister()
1445 	v4l2_device_unregister(&vin->v4l2_dev);  in rvin_dma_unregister()
1448 int rvin_dma_register(struct rvin_dev *vin, int irq)  in rvin_dma_register()  argument
1450 	struct vb2_queue *q = &vin->queue;  in rvin_dma_register()
1454 	ret = v4l2_device_register(vin->dev, &vin->v4l2_dev);  in rvin_dma_register()
1458 	mutex_init(&vin->lock);  in rvin_dma_register()
1459 	INIT_LIST_HEAD(&vin->buf_list);  in rvin_dma_register()
1461 	spin_lock_init(&vin->qlock);  in rvin_dma_register()
1464 		vin->buf_hw[i].buffer = NULL;  in rvin_dma_register()
1469 	q->lock = &vin->lock;  in rvin_dma_register()
1470 	q->drv_priv = vin;  in rvin_dma_register()
1476 	q->dev = vin->dev;  in rvin_dma_register()
1480 		vin_err(vin, "failed to initialize VB2 queue\n");  in rvin_dma_register()
1485 	ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED,  in rvin_dma_register()
1486 			       KBUILD_MODNAME, vin);  in rvin_dma_register()
1488 		vin_err(vin, "failed to request irq\n");  in rvin_dma_register()
1494 	rvin_dma_unregister(vin);  in rvin_dma_register()
1505  * as it's only possible to do so when no VIN in the group is
1508 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)  in rvin_set_channel_routing()  argument
1515 	ret = pm_runtime_resume_and_get(vin->dev);  in rvin_set_channel_routing()
1520 	vnmc = rvin_read(vin, VNMC_REG);  in rvin_set_channel_routing()
1521 	rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);  in rvin_set_channel_routing()
1529 	for (route = vin->info->routes; route->chsel; route++) {  in rvin_set_channel_routing()
1541 		rvin_write(vin, ifmd, VNCSI_IFMD_REG);  in rvin_set_channel_routing()
1544 	vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);  in rvin_set_channel_routing()
1546 	vin->chsel = chsel;  in rvin_set_channel_routing()
1549 	rvin_write(vin, vnmc, VNMC_REG);  in rvin_set_channel_routing()
1551 	pm_runtime_put(vin->dev);  in rvin_set_channel_routing()
1556 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha)  in rvin_set_alpha()  argument
1561 	spin_lock_irqsave(&vin->qlock, flags);  in rvin_set_alpha()
1563 	vin->alpha = alpha;  in rvin_set_alpha()
1565 	if (!vin->running)  in rvin_set_alpha()
1568 	switch (vin->format.pixelformat) {  in rvin_set_alpha()
1570 		dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT;  in rvin_set_alpha()
1571 		if (vin->alpha)  in rvin_set_alpha()
1575 		dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK;  in rvin_set_alpha()
1576 		dmr |= VNDMR_A8BIT(vin->alpha);  in rvin_set_alpha()
1582 	rvin_write(vin, dmr,  VNDMR_REG);  in rvin_set_alpha()
1584 	spin_unlock_irqrestore(&vin->qlock, flags);  in rvin_set_alpha()