13 #define WRAPPER_TZ_BASE_OFFS			0x000C0000
14 #define AON_BASE_OFFS				0x000E0000
15 #define AON_MVP_NOC_RESET			0x0001F000
17 #define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
18 #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
19 #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
20 #define REQ_POWER_DOWN_PREP			BIT(0)
21 #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
22 #define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)
23 #define CORE_CLK_RUN				0x0
25 #define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
26 #define CTL_AXI_CLK_HALT			BIT(0)
29 #define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
30 #define RESET_HIGH				BIT(0)
32 #define CPU_CS_AHB_BRIDGE_SYNC_RESET		(CPU_CS_BASE_OFFS + 0x160)
33 #define CORE_BRIDGE_SW_RESET			BIT(0)
36 #define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
37 #define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
40 #define AON_WRAPPER_MVP_NOC_RESET_REQ		(AON_MVP_NOC_RESET + 0x000)
41 #define VIDEO_NOC_RESET_REQ			(BIT(0) | BIT(1))
43 #define AON_WRAPPER_MVP_NOC_RESET_ACK		(AON_MVP_NOC_RESET + 0x004)
45 #define VCODEC_SS_IDLE_STATUSN			(VCODEC_BASE_OFFS + 0x70)
48 #define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
50 #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET	(AON_BASE_OFFS + 0x18)
51 #define SW_RESET				BIT(0)
52 #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL	(AON_BASE_OFFS + 0x20)
53 #define NOC_HALT				BIT(0)
54 #define AON_WRAPPER_SPARE			(AON_BASE_OFFS + 0x28)
68 	u32 reg_val = 0, value, i;  in iris_vpu3_power_off_hardware()
80 	for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {  in iris_vpu3_power_off_hardware()
82 					 reg_val, reg_val & 0x400000, 2000, 20000);  in iris_vpu3_power_off_hardware()
90 				 reg_val, reg_val & 0x3, 200, 2000);  in iris_vpu3_power_off_hardware()
94 	writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);  in iris_vpu3_power_off_hardware()
97 				 reg_val, !(reg_val & 0x3), 200, 2000);  in iris_vpu3_power_off_hardware()
104 	writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);  in iris_vpu3_power_off_hardware()
112 	u32 reg_val = 0, value, i;  in iris_vpu33_power_off_hardware()
124 	for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {  in iris_vpu33_power_off_hardware()
126 					 reg_val, reg_val & 0x400000, 2000, 20000);  in iris_vpu33_power_off_hardware()
132 				 reg_val, reg_val & BIT(0), 200, 2000);  in iris_vpu33_power_off_hardware()
136 	/* set MNoC to low power, set PD_NOC_QREQ (bit 0) */  in iris_vpu33_power_off_hardware()
137 	writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);  in iris_vpu33_power_off_hardware()
142 	writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);  in iris_vpu33_power_off_hardware()
152 	u32 val = 0;  in iris_vpu33_power_off_controller()
160 				 val, val & BIT(0), 200, 2000);  in iris_vpu33_power_off_controller()
164 	writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);  in iris_vpu33_power_off_controller()
167 				 val, val == 0, 200, 2000);  in iris_vpu33_power_off_controller()
174 	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);  in iris_vpu33_power_off_controller()
175 	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);  in iris_vpu33_power_off_controller()
191 				 val, (val & BIT(0)) == 0, 1000, 50000);  in iris_vpu33_power_off_controller()
212 	writel(0, core->reg_base + AON_WRAPPER_SPARE);  in iris_vpu33_power_off_controller()
225 	return 0;  in iris_vpu33_power_off_controller()