Lines Matching defs:vfe
3 * camss-vfe-4-8.c
17 #include "camss-vfe.h"
18 #include "camss-vfe-gen1.h"
248 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits)
250 u32 bits = readl_relaxed(vfe->base + reg);
252 writel_relaxed(bits & ~clr_bits, vfe->base + reg);
255 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
257 u32 bits = readl_relaxed(vfe->base + reg);
259 writel_relaxed(bits | set_bits, vfe->base + reg);
262 static void vfe_global_reset(struct vfe_device *vfe)
275 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0);
279 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
282 static void vfe_halt_request(struct vfe_device *vfe)
285 vfe->base + VFE_0_BUS_BDG_CMD);
288 static void vfe_halt_clear(struct vfe_device *vfe)
290 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
293 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable)
296 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm),
299 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm),
358 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm,
374 writel_relaxed(reg, vfe->base +
383 writel_relaxed(reg, vfe->base +
386 writel_relaxed(0, vfe->base +
388 writel_relaxed(0, vfe->base +
393 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per)
397 reg = readl_relaxed(vfe->base +
406 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm));
409 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm,
412 writel_relaxed(pattern, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm));
415 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm,
422 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm));
425 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm)
430 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD);
436 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr)
439 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm));
442 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr)
445 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm));
448 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm)
452 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS);
457 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable)
460 writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);
462 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);
465 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm,
471 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg);
476 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg);
497 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg);
500 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm)
503 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm));
506 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm,
512 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg);
533 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg);
536 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output,
555 vfe_reg_set(vfe,
559 vfe_reg_clr(vfe,
571 vfe_reg_set(vfe,
575 vfe_reg_clr(vfe,
593 vfe_reg_set(vfe,
597 vfe_reg_clr(vfe,
606 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line,
617 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val);
619 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val);
630 writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG);
633 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid)
635 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id),
638 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id),
642 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
644 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id);
649 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE);
655 static inline void vfe_reg_update_clear(struct vfe_device *vfe,
658 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id);
661 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm,
670 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0);
671 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1);
673 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0);
674 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1);
678 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp,
681 struct vfe_output *output = &vfe->line[line_id].output;
698 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0);
699 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1);
700 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask);
702 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0);
703 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1);
704 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask);
708 static void vfe_enable_irq_common(struct vfe_device *vfe)
714 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0);
715 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1);
718 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line)
722 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG);
725 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0);
728 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1);
750 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG);
751 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG);
754 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line)
762 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);
767 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE);
772 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE);
777 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE);
782 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE);
784 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);
789 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE);
794 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE);
801 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE);
806 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE);
809 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line)
818 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH);
823 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT);
828 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH);
837 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT);
840 static void vfe_set_clamp_cfg(struct vfe_device *vfe)
846 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG);
852 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG);
855 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable)
860 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line)
881 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG);
885 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG);
888 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG);
891 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG);
894 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG);
897 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN);
900 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN);
903 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val);
906 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG);
909 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable)
914 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
924 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
927 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable)
935 vfe_reg_set(vfe, VFE_0_MODULE_LENS_EN, val_lens);
936 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom);
938 vfe_reg_clr(vfe, VFE_0_MODULE_LENS_EN, val_lens);
939 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom);
943 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev)
948 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS,
968 struct vfe_device *vfe = dev;
972 vfe->res->hw_ops->isr_read(vfe, &value0, &value1);
974 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n",
978 vfe->isr_ops.reset_ack(vfe);
981 vfe->res->hw_ops->violation_read(vfe);
984 vfe->isr_ops.halt_ack(vfe);
986 for (i = VFE_LINE_RDI0; i < vfe->res->line_num; i++)
988 vfe->isr_ops.reg_update(vfe, i);
991 vfe->isr_ops.sof(vfe, VFE_LINE_PIX);
995 vfe->isr_ops.sof(vfe, i);
999 vfe->isr_ops.comp_done(vfe, i);
1000 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++)
1001 if (vfe->wm_output_map[j] == VFE_LINE_PIX)
1007 vfe->isr_ops.wm_done(vfe, i);
1018 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable)
1022 vfe->base + VFE_0_BUS_IMAGE_MASTER_CMD);
1025 vfe->base + VFE_0_BUS_IMAGE_MASTER_CMD);
1031 static void vfe_set_qos(struct vfe_device *vfe)
1038 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0);
1039 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1);
1040 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2);
1041 writel_relaxed(val3, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3);
1042 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4);
1043 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5);
1044 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6);
1045 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);
1048 static void vfe_set_ds(struct vfe_device *vfe)
1053 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0);
1054 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1);
1055 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2);
1056 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3);
1057 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4);
1058 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5);
1059 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6);
1060 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7);
1061 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8);
1062 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9);
1063 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10);
1064 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11);
1065 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12);
1066 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13);
1067 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14);
1068 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15);
1069 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16);
1072 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1)
1074 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0);
1075 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1);
1077 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0);
1078 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1);
1082 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD);
1085 static void vfe_violation_read(struct vfe_device *vfe)
1087 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS);
1129 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
1131 vfe->isr_ops = vfe_isr_ops_gen1;
1132 vfe->ops_gen1 = &vfe_ops_gen1_4_8;
1133 vfe->video_ops = vfe_video_ops_gen1;