chips-media/wave5/wave5-hw.c

53 static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason,
93 static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason,
96 	struct device *dev = vpu_dev->dev;
101 		reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON);
131 static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val)
137 	wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl);
139 				0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR);
143 	if (wave5_vdi_read_register(vpu_dev, W5_VPU_FIO_DATA) != val)
149 static void wave5_fio_writel(struct vpu_device *vpu_dev, unsigned int addr, unsigned int data)
154 	wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_DATA, data);
157 	wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl);
159 				FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR);
161 		dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n",
165 static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr)
169 	if (vpu_dev->product_code == WAVE515_CODE)
171 	if (vpu_dev->product_code == WAVE521C_CODE ||
172 	    vpu_dev->product_code == WAVE521_CODE ||
173 	    vpu_dev->product_code == WAVE521E1_CODE)
176 	return wave5_wait_fio_readl(vpu_dev, addr, gdi_status_check_value);
179 static int wave5_wait_vpu_busy(struct vpu_device *vpu_dev, unsigned int addr)
184 				 0, VPU_BUSY_CHECK_TIMEOUT, false, vpu_dev, addr);
187 static int wave5_wait_vcpu_bus_busy(struct vpu_device *vpu_dev, unsigned int addr)
189 	return wave5_wait_fio_readl(vpu_dev, addr, 0);
192 bool wave5_vpu_is_init(struct vpu_device *vpu_dev)
194 	return vpu_read_reg(vpu_dev, W5_VCPU_CUR_PC) != 0;
197 unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev)
199 	u32 val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER);
212 		dev_err(vpu_dev->dev, "Unsupported product id (%x)\n", val);
215 		dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val);
222 static void wave5_bit_issue_command(struct vpu_device *vpu_dev, struct vpu_instance *inst, u32 cmd)
231 		vpu_write_reg(vpu_dev, W5_CMD_INSTANCE_INFO, (codec_mode << 16) |
233 		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
236 	vpu_write_reg(vpu_dev, W5_COMMAND, cmd);
239 		dev_dbg(vpu_dev->dev, "%s: cmd=0x%x (%s)\n", __func__, cmd,
242 		dev_dbg(vpu_dev->dev, "%s: cmd=0x%x\n", __func__, cmd);
245 	vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1);
299 static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *inst,
304 	vpu_write_reg(vpu_dev, W5_QUERY_OPTION, query_opt);
305 	vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
306 	wave5_bit_issue_command(vpu_dev, inst, W5_QUERY);
308 	ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);
310 		dev_warn(vpu_dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt);
314 	return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL);
317 static void setup_wave5_interrupts(struct vpu_device *vpu_dev)
321 	if (vpu_dev->attr.support_encoders) {
328 	if (vpu_dev->attr.support_decoders) {
335 	return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
340 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
341 	struct vpu_attr *p_attr = &vpu_dev->attr;
347 	ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO);
351 	reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME);
359 	p_attr->product_id = wave5_vpu_get_product_id(vpu_dev);
360 	p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION);
361 	p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION);
362 	p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID);
363 	hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0);
364 	hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1);
365 	hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE);
367 	if (vpu_dev->product_code == WAVE515_CODE) {
395 	setup_wave5_interrupts(vpu_dev);
400 int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision)
405 	ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO);
409 	reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION);
418 static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index)
420 	vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, REMAP_CTRL_REGISTER_VALUE(index));
421 	vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE);
422 	vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE);
432 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
434 	common_vb = &vpu_dev->common_mem;
438 	if (vpu_dev->product_code == WAVE515_CODE)
451 	ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size);
453 		dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n",
458 	vpu_write_reg(vpu_dev, W5_PO_CONF, 0);
463 		vpu_write_reg(vpu_dev, i, 0x00);
465 	remap_page(vpu_dev, code_base, W5_REMAP_INDEX0);
466 	remap_page(vpu_dev, code_base, W5_REMAP_INDEX1);
468 	vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);
469 	vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);
470 	vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0);
471 	vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base);
472 	vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size);
475 	vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);
477 	if (vpu_dev->product_code != WAVE515_CODE) {
478 		wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0);
479 		wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
480 		vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
483 	reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
493 		wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);
496 	if (vpu_dev->product_code == WAVE515_CODE) {
499 		vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, WAVE515_COMMAND_QUEUE_DEPTH);
500 		vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, WAVE515_ONE_TASKBUF_SIZE);
505 			vpu_write_reg(vpu_dev,
510 		vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
511 		vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
514 	vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
515 	vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU);
516 	vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);
517 	ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);
519 		dev_err(vpu_dev->dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n");
523 	ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code);
535 	struct vpu_device *vpu_dev = inst->dev;
538 	if (vpu_dev->sram_buf.size) {
554 	if (vpu_dev->product == PRODUCT_ID_515)
572 		vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
573 		vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
591 		wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work);
1012 	struct vpu_device *vpu_dev = inst->dev;
1019 	ret = wave5_send_query(vpu_dev, inst, GET_RESULT);
1093 		vpu_dev->last_performance_cycles = result->dec_decode_end_tick;
1097 			(result->dec_decode_end_tick - vpu_dev->last_performance_cycles) *
1099 		vpu_dev->last_performance_cycles = result->dec_decode_end_tick;
1100 		if (vpu_dev->last_performance_cycles < result->dec_host_cmd_tick)
1120 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
1122 	common_vb = &vpu_dev->common_mem;
1126 	if (vpu_dev->product_code == WAVE515_CODE)
1139 	old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR);
1144 		ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size);
1146 			dev_err(vpu_dev->dev,
1151 		vpu_write_reg(vpu_dev, W5_PO_CONF, 0);
1155 			dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret);
1159 		remap_page(vpu_dev, code_base, W5_REMAP_INDEX0);
1160 		remap_page(vpu_dev, code_base, W5_REMAP_INDEX1);
1162 		vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);
1163 		vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);
1164 		vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0);
1165 		vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base);
1166 		vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size);
1169 		vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);
1171 		if (vpu_dev->product_code != WAVE515_CODE) {
1172 			wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0);
1173 			wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
1174 			vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
1177 		reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
1187 			wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);
1190 		if (vpu_dev->product_code == WAVE515_CODE) {
1194 			vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF,
1196 			vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE,
1202 				vpu_write_reg(vpu_dev,
1207 			vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI,
1208 				      vpu_dev->sram_buf.daddr);
1209 			vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE,
1210 				      vpu_dev->sram_buf.size);
1213 		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
1214 		vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU);
1215 		vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);
1217 		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);
1219 			dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n");
1223 		ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code);
1238 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
1242 		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);
1251 		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
1252 		vpu_write_reg(vpu_dev, W5_COMMAND, W5_SLEEP_VPU);
1254 		vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1);
1256 		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);
1260 		ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code);
1264 		common_vb = &vpu_dev->common_mem;
1268 		if (vpu_dev->product_code == WAVE515_CODE)
1284 		vpu_write_reg(vpu_dev, W5_PO_CONF, 0);
1286 		remap_page(vpu_dev, code_base, W5_REMAP_INDEX0);
1287 		remap_page(vpu_dev, code_base, W5_REMAP_INDEX1);
1289 		vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);
1290 		vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);
1291 		vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0);
1294 		vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);
1296 		if (vpu_dev->product_code != WAVE515_CODE) {
1297 			wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0);
1298 			wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
1299 			vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
1302 		setup_wave5_interrupts(vpu_dev);
1304 		reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
1314 			wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);
1317 		if (vpu_dev->product_code == WAVE515_CODE) {
1321 			vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF,
1323 			vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE,
1329 				vpu_write_reg(vpu_dev,
1334 			vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI,
1335 				      vpu_dev->sram_buf.daddr);
1336 			vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE,
1337 				      vpu_dev->sram_buf.size);
1340 		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
1341 		vpu_write_reg(vpu_dev, W5_COMMAND, W5_WAKEUP_VPU);
1343 		vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);
1345 		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);
1347 			dev_err(vpu_dev->dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n");
1351 		return wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code);
1361 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
1362 	struct vpu_attr *p_attr = &vpu_dev->attr;
1364 	vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0);
1372 	val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
1387 				wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0xFF);
1390 				ret = wave5_wait_vcpu_bus_busy(vpu_dev,
1393 					wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00);
1398 			wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7);
1401 			if (wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0)) {
1402 				wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
1407 			wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7);
1410 			if (wave5_wait_bus_busy(vpu_dev, W5_COMBINED_BACKBONE_BUS_STATUS)) {
1411 				wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);
1418 		wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x100);
1421 		ret = wave5_wait_bus_busy(vpu_dev, W5_GDI_BUS_STATUS);
1423 			wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00);
1439 		vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, val);
1441 		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_RESET_STATUS);
1443 			vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0);
1446 		vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0);
1452 				wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00);
1453 			wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
1455 			wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);
1458 		wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00);
1556 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
1561 	if (vpu_dev->sram_buf.size) {
1567 	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work);
1573 	wave5_vdi_clear_memory(vpu_dev, &p_enc_info->vb_work);
1578 	vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
1579 	vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
1608 	if (wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work))
1936 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
2007 	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_mv);
2018 	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_y_tbl);
2026 	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_c_tbl);
2038 	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_sub_sam_buf);
2048 		ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_task);
2114 	ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL);
2121 	wave5_vdi_free_dma_memory(vpu_dev, &vb_task);
2123 	wave5_vdi_free_dma_memory(vpu_dev, &vb_sub_sam_buf);
2125 	wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_c_tbl);
2127 	wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_y_tbl);
2129 	wave5_vdi_free_dma_memory(vpu_dev, &vb_mv);
2341 	struct vpu_device *vpu_dev = inst->dev;
2397 			(result->enc_encode_end_tick - vpu_dev->last_performance_cycles) *
2399 		if (vpu_dev->last_performance_cycles < result->enc_host_cmd_tick)
2403 	vpu_dev->last_performance_cycles = result->enc_encode_end_tick;
2418 	struct vpu_device *vpu_dev = inst->dev;
2419 	struct device *dev = vpu_dev->dev;
2539 static bool wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev,
2547 			dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n");
2548 			dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n");
2553 			dev_err(vpu_dev->dev,