Lines Matching defs:s
108 struct cx18_stream *s = vb2_get_drv_priv(vq);
109 struct cx18 *cx = s->cx;
116 if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16)
122 * Let's request at least three buffers: two for the
141 struct cx18_stream *s = vb2_get_drv_priv(vb->vb2_queue);
147 spin_lock_irqsave(&s->vb_lock, flags);
148 list_add_tail(&buf->list, &s->vb_capture);
149 spin_unlock_irqrestore(&s->vb_lock, flags);
155 struct cx18_stream *s = vb2_get_drv_priv(vb->vb2_queue);
156 struct cx18 *cx = s->cx;
163 if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16)
175 void cx18_clear_queue(struct cx18_stream *s, enum vb2_buffer_state state)
177 while (!list_empty(&s->vb_capture)) {
180 buf = list_first_entry(&s->vb_capture,
190 struct cx18_stream *s = vb2_get_drv_priv(vq);
199 s->sequence = 0;
203 mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
208 spin_lock_irqsave(&s->vb_lock, flags);
209 cx18_clear_queue(s, VB2_BUF_STATE_QUEUED);
210 spin_unlock_irqrestore(&s->vb_lock, flags);
216 struct cx18_stream *s = vb2_get_drv_priv(vq);
219 cx18_stop_capture(s, 0);
220 timer_delete_sync(&s->vb_timeout);
221 spin_lock_irqsave(&s->vb_lock, flags);
222 cx18_clear_queue(s, VB2_BUF_STATE_ERROR);
223 spin_unlock_irqrestore(&s->vb_lock, flags);
236 struct cx18_stream *s = &cx->streams[type];
239 memset(s, 0, sizeof(*s));
242 s->dvb = NULL;
243 s->cx = cx;
244 s->type = type;
245 s->name = cx18_stream_info[type].name;
246 s->handle = CX18_INVALID_TASK_HANDLE;
248 s->dma = cx18_stream_info[type].dma;
249 s->v4l2_dev_caps = cx18_stream_info[type].caps;
250 s->buffers = cx->stream_buffers[type];
251 s->buf_size = cx->stream_buf_size[type];
252 INIT_LIST_HEAD(&s->buf_pool);
253 s->bufs_per_mdl = 1;
254 s->mdl_size = s->buf_size * s->bufs_per_mdl;
256 init_waitqueue_head(&s->waitq);
257 s->id = -1;
258 spin_lock_init(&s->q_free.lock);
259 cx18_queue_init(&s->q_free);
260 spin_lock_init(&s->q_busy.lock);
261 cx18_queue_init(&s->q_busy);
262 spin_lock_init(&s->q_full.lock);
263 cx18_queue_init(&s->q_full);
264 spin_lock_init(&s->q_idle.lock);
265 cx18_queue_init(&s->q_idle);
267 INIT_WORK(&s->out_work_order, cx18_out_work_handler);
269 INIT_LIST_HEAD(&s->vb_capture);
270 timer_setup(&s->vb_timeout, cx18_vb_timeout, 0);
271 spin_lock_init(&s->vb_lock);
274 s->vb_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
277 s->pixelformat = V4L2_PIX_FMT_NV12_16L16;
278 s->vb_bytes_per_frame = cx->cxhdl.height * 720 * 3 / 2;
279 s->vb_bytes_per_line = 720;
281 s->vidq.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
282 s->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
283 s->vidq.drv_priv = s;
284 s->vidq.buf_struct_size = sizeof(struct cx18_vb2_buffer);
285 s->vidq.ops = &cx18_vb2_qops;
286 s->vidq.mem_ops = &vb2_vmalloc_memops;
287 s->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
288 s->vidq.min_queued_buffers = 2;
289 s->vidq.gfp_flags = GFP_DMA32;
290 s->vidq.dev = &cx->pci_dev->dev;
291 s->vidq.lock = &cx->serialize_lock;
293 err = vb2_queue_init(&s->vidq);
296 s->video_dev.queue = &s->vidq;
303 struct cx18_stream *s = &cx->streams[type];
316 s->video_dev.v4l2_dev = NULL;
317 s->dvb = NULL;
318 s->cx = cx;
319 s->type = type;
320 s->name = cx18_stream_info[type].name;
335 CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name);
346 s->dvb = kzalloc(sizeof(struct cx18_dvb), GFP_KERNEL);
347 if (s->dvb == NULL) {
348 CX18_ERR("Couldn't allocate cx18_dvb structure for %s\n",
349 s->name);
354 s->buffers = 0;
362 snprintf(s->video_dev.name, sizeof(s->video_dev.name), "%s %s",
363 cx->v4l2_dev.name, s->name);
365 s->video_dev.num = num;
366 s->video_dev.v4l2_dev = &cx->v4l2_dev;
368 s->video_dev.fops = &cx18_v4l2_enc_yuv_fops;
370 s->video_dev.fops = &cx18_v4l2_enc_fops;
371 s->video_dev.release = video_device_release_empty;
373 s->video_dev.tvnorms = cx->tuner_std;
375 s->video_dev.tvnorms = V4L2_STD_ALL;
376 s->video_dev.lock = &cx->serialize_lock;
377 cx18_set_funcs(&s->video_dev);
408 struct cx18_stream *s = &cx->streams[type];
413 if (type == CX18_ENC_STREAM_TYPE_TS && s->dvb != NULL) {
414 ret = cx18_dvb_register(s);
421 if (s->video_dev.v4l2_dev == NULL)
424 num = s->video_dev.num;
425 s->video_dev.device_caps = s->v4l2_dev_caps; /* device capabilities */
434 video_set_drvdata(&s->video_dev, s);
437 ret = video_register_device_no_warn(&s->video_dev, vfl_type, num);
439 CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n",
440 s->name, num);
441 s->video_dev.v4l2_dev = NULL;
445 name = video_device_node_name(&s->video_dev);
449 CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n",
450 name, s->name, cx->stream_buffers[type],
456 CX18_INFO("Registered device %s for %s\n", name, s->name);
461 CX18_INFO("Registered device %s for %s (%d x %d bytes)\n",
462 name, s->name, cx->stream_buffers[type],
465 CX18_INFO("Registered device %s for %s\n",
466 name, s->name);
548 static void cx18_vbi_setup(struct cx18_stream *s)
550 struct cx18 *cx = s->cx;
584 * The EAV RP code's Field bit toggles on line 4, a few lines
590 * The EAV RP code's Field bit toggles on line 1, a few lines
599 data[0] = s->handle;
660 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
663 if (!cx18_stream_enabled(s))
667 if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >=
672 if (atomic_read(&s->q_full.depth) < 2)
679 mdl = cx18_dequeue(s, &s->q_full);
681 cx18_enqueue(s, mdl, &s->q_free);
685 struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s,
688 struct cx18 *cx = s->cx;
692 if (s->handle == CX18_INVALID_TASK_HANDLE ||
693 test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
694 !test_bit(CX18_F_S_STREAMING, &s->s_flags))
695 return cx18_enqueue(s, mdl, &s->q_free);
697 q = cx18_enqueue(s, mdl, &s->q_busy);
698 if (q != &s->q_busy)
701 cx18_mdl_sync_for_device(s, mdl);
702 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
704 s->bufs_per_mdl, mdl->id, s->mdl_size);
709 void _cx18_stream_load_fw_queue(struct cx18_stream *s)
714 if (atomic_read(&s->q_free.depth) == 0 ||
715 atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
720 mdl = cx18_dequeue(s, &s->q_free);
723 q = _cx18_stream_put_mdl_fw(s, mdl);
724 } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM
725 && q == &s->q_busy);
730 struct cx18_stream *s =
733 _cx18_stream_load_fw_queue(s);
736 static void cx18_stream_configure_mdls(struct cx18_stream *s)
738 cx18_unload_queues(s);
740 switch (s->type) {
747 if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16)
748 s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2;
750 s->mdl_size = 720 * s->cx->cxhdl.height * 2;
751 s->bufs_per_mdl = s->mdl_size / s->buf_size;
752 if (s->mdl_size % s->buf_size)
753 s->bufs_per_mdl++;
756 s->bufs_per_mdl = 1;
757 if (cx18_raw_vbi(s->cx)) {
758 s->mdl_size = (s->cx->is_60hz ? 12 : 18)
766 s->mdl_size = s->cx->is_60hz
772 s->bufs_per_mdl = 1;
773 s->mdl_size = s->buf_size * s->bufs_per_mdl;
777 cx18_load_queues(s);
780 int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
783 struct cx18 *cx = s->cx;
787 if (!cx18_stream_enabled(s))
790 CX18_DEBUG_INFO("Start encoder stream %s\n", s->name);
792 switch (s->type) {
834 clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
837 s->handle = data[0];
838 cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype);
846 * channel types. We're hoping there's no harm in calling most of them
852 cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0);
853 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1);
854 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0);
855 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1);
863 s->handle, 12);
872 s->handle, 312, 313);
875 cx18_vbi_setup(s);
884 s->handle, cx18_stream_enabled(s_idx) ? 7 : 0);
887 cx->cxhdl.priv = s;
896 cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
903 if (s->pixelformat == V4L2_PIX_FMT_UYVY)
905 s->handle, 1);
909 s->handle, 0);
919 cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle,
920 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem,
921 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem);
924 cx18_stream_configure_mdls(s);
925 _cx18_stream_load_fw_queue(s);
928 if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
931 set_bit(CX18_F_S_STOPPING, &s->s_flags);
932 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
933 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
935 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
936 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
938 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
939 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
940 s->handle = CX18_INVALID_TASK_HANDLE;
941 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
962 struct cx18_stream *s = &cx->streams[i];
964 if (!cx18_stream_enabled(s))
966 if (test_bit(CX18_F_S_STREAMING, &s->s_flags))
967 cx18_stop_v4l2_encode_stream(s, 0);
971 int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
973 struct cx18 *cx = s->cx;
975 if (!cx18_stream_enabled(s))
986 set_bit(CX18_F_S_STOPPING, &s->s_flags);
987 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
988 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
990 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
992 if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) {
996 if (s->type != CX18_ENC_STREAM_TYPE_TS)
1001 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
1004 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
1006 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
1007 s->handle = CX18_INVALID_TASK_HANDLE;
1008 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
1015 wake_up(&s->waitq);
1027 struct cx18_stream *s = &cx->streams[i];
1029 if (s->video_dev.v4l2_dev && (s->handle != CX18_INVALID_TASK_HANDLE))
1030 return s->handle;
1038 struct cx18_stream *s;
1044 s = &cx->streams[i];
1045 if (s->handle != handle)
1047 if (cx18_stream_enabled(s))
1048 return s;