pci/cx18/cx18-av-firmware.c

22 static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
24 	struct v4l2_subdev *sd = &cx->av_state.sd;
32 	dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
36 		cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
37 		dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
42 		dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
55 		dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
63 int cx18_av_loadfw(struct cx18 *cx)
65 	struct v4l2_subdev *sd = &cx->av_state.sd;
73 	if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) {
81 		cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
83 		cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
86 		cx18_av_write4_expect(cx, 0x8100, 0x00010000,
90 		cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
103 				cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
106 				value = cx18_av_read4(cx, CXADEC_DL_CTL);
130 	cx18_av_write4_expect(cx, CXADEC_DL_CTL,
135 	if (cx18_av_verifyfw(cx, fw) == 0)
136 		cx18_av_write4_expect(cx, CXADEC_DL_CTL,
140 	cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
147 	cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
156 	cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
160 	cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
162 	cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
169 	cx18_av_write4(cx, 0x09CC, 1);
171 	v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
174 		cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
178 	v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
184 		cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
191 		cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
196 	cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
200 	v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
204 	cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);