media/i2c/adv7604.c

621 #define ADV76XX_REG(page, offset)	(((page) << 8) | (offset))
3008 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
3009 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
3010 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
3011 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
3012 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
3013 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
3014 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
3015 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
3016 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
3017 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
3018 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
3019 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
3023 	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
3024 	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
3025 	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
3026 	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
3027 	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
3035 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
3036 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
3037 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
3038 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
3039 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
3040 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
3041 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
3042 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
3043 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
3044 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
3045 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
3049 	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
3050 	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
3057 	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3058 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3059 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3060 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3061 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3062 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3063 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3064 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3065 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3066 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
3067 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
3073 	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3074 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3075 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3076 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3077 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3078 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3079 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3080 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3081 	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },