Lines Matching +full:sp +full:- +full:disabled +full:- +full:ports
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
7 * Peter Sprenger (sprengermoving-bytes.de)
9 * inspired by existing hfc-pci driver:
10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
22 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
23 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
24 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
26 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
38 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
41 * port: (optional or required for all ports on all installed cards)
42 * HFC-4S/HFC-8S only bits:
47 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
48 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
51 * HFC-E1 only bits:
53 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
58 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
64 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
88 * -1 means no support of PCM bus not even.
93 * NOTE: One dmask value must be given for every HFC-E1 card.
94 * If omitted, the E1 card has D-channel on time slot 16, which is default.
98 * value stands for a B-channel. The bmask may not overlap with dmask or
101 * This will create one fragment with D-channel on slot 1 with
102 * B-channels on slots 2..15, and a second fragment with D-channel
103 * on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
104 * If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
108 * B-channels.
109 * If no bits are set on bmask, no B-channel is created for that fragment.
110 * Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
111 * This will create 31 ports with one D-channel only.
116 * -> See hfc_multi.h for HFC_IO_MODE_* values
138 * Set to card number starting with 1. Set to -1 to disable.
224 MODULE_DESCRIPTION("mISDN driver for hfc-4s/hfc-8s/hfc-e1 based cards");
243 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
245 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
247 (hc->HFC_inb(hc, reg, __func__, __LINE__))
249 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
251 (hc->HFC_inw(hc, reg, __func__, __LINE__))
253 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
255 (hc->HFC_wait(hc, __func__, __LINE__))
257 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
259 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
260 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
261 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
262 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
263 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
264 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
265 #define HFC_wait(hc) (hc->HFC_wait(hc))
266 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
282 writeb(val, hc->pci_membase + reg);
291 return readb(hc->pci_membase + reg);
300 return readw(hc->pci_membase + reg);
309 while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
322 outb(reg, hc->pci_iobase + 4);
323 outb(val, hc->pci_iobase);
332 outb(reg, hc->pci_iobase + 4);
333 return inb(hc->pci_iobase);
342 outb(reg, hc->pci_iobase + 4);
343 return inw(hc->pci_iobase);
352 outb(R_STATUS, hc->pci_iobase + 4);
353 while (inb(hc->pci_iobase) & V_BUSY)
365 i = -1;
383 hc->id, reg, regname, val, bits, function, line);
413 hc->id, reg, regname, val, bits, function, line);
435 hc->id, reg, regname, val, function, line);
442 hc->id, function, line);
451 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
453 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
455 len -= 4;
458 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
460 len -= 2;
463 outb(*data, hc->pci_iobase);
465 len--;
474 hc->pci_membase + A_FIFO_DATA0);
476 len -= 4;
480 hc->pci_membase + A_FIFO_DATA0);
482 len -= 2;
485 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
487 len--;
495 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
497 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
499 len -= 4;
502 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
504 len -= 2;
507 *data = inb(hc->pci_iobase);
509 len--;
519 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
521 len -= 4;
525 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
527 len -= 2;
530 *data = readb(hc->pci_membase + A_FIFO_DATA0);
532 len--;
539 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
540 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
546 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
547 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
572 if (!hc->pci_iobase)
585 outw(cipv, hc->pci_iobase + 4);
586 data = inb(hc->pci_iobase);
600 if (!hc->pci_iobase)
609 outw(cipv, hc->pci_iobase + 4);
621 outl(datav, hc->pci_iobase);
722 /* Setup TDM path - sets fsync and tdm_clk as inputs */
736 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
739 printk(KERN_DEBUG "VPM: A-law mode\n");
758 * reference at link-time.
814 struct bchannel *bch = hc->chan[ch].bch;
816 int txadj = -4;
819 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
846 struct bchannel *bch = hc->chan[ch].bch;
852 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
902 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
903 if (hc->syncronized) {
913 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
914 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
918 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
920 if (hc->ctype == HFC_TYPE_E1) {
924 hc->e1_resync |= 1; /* get SYNC_I */
934 "interface.\n", hc->id, hc);
936 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
940 /* switch to jatt PLL, if not disabled by RX_SYNC */
941 if (hc->ctype == HFC_TYPE_E1
942 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
945 hc->e1_resync |= 2; /* switch to jatt */
953 "with QUARTZ\n", hc->id, hc);
954 if (hc->ctype == HFC_TYPE_E1) {
959 "Schedule QUARTZ for HFC-E1\n");
960 hc->e1_resync |= 4; /* switch quartz */
965 "enabled by HFC-%dS\n", hc->ctype);
967 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
986 if (hc->syncronized) {
990 " (id=%d)\n", __func__, hc->id + 1,
991 hc->id);
998 " (id=%d)\n", __func__, hc->id + 1,
999 hc->id);
1020 hc->hw.r_cirm |= V_SRES;
1021 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1023 hc->hw.r_cirm &= ~V_SRES;
1024 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1028 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1031 __func__, hc->id + 1);
1033 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1051 /* disable memory mapped ports / io ports */
1052 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1053 if (hc->pci_dev)
1054 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1055 if (hc->pci_membase)
1056 iounmap(hc->pci_membase);
1057 if (hc->plx_membase)
1058 iounmap(hc->plx_membase);
1059 if (hc->pci_iobase)
1060 release_region(hc->pci_iobase, 8);
1061 if (hc->xhfc_membase)
1062 iounmap((void *)hc->xhfc_membase);
1064 if (hc->pci_dev) {
1065 pci_disable_device(hc->pci_dev);
1066 pci_set_drvdata(hc->pci_dev, NULL);
1089 spin_lock_irqsave(&hc->lock, flags);
1091 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1100 err = -EIO;
1106 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1108 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1109 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1123 /* set s-ram size */
1124 hc->Flen = 0x10;
1125 hc->Zmin = 0x80;
1126 hc->Zlen = 384;
1127 hc->DTMFbase = 0x1000;
1128 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1132 hc->hw.r_ctrl |= V_EXT_RAM;
1133 hc->hw.r_ram_sz = 1;
1134 hc->Flen = 0x20;
1135 hc->Zmin = 0xc0;
1136 hc->Zlen = 1856;
1137 hc->DTMFbase = 0x2000;
1139 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1143 hc->hw.r_ctrl |= V_EXT_RAM;
1144 hc->hw.r_ram_sz = 2;
1145 hc->Flen = 0x20;
1146 hc->Zmin = 0xc0;
1147 hc->Zlen = 8000;
1148 hc->DTMFbase = 0x2000;
1150 if (hc->ctype == HFC_TYPE_XHFC) {
1151 hc->Flen = 0x8;
1152 hc->Zmin = 0x0;
1153 hc->Zlen = 64;
1154 hc->DTMFbase = 0x0;
1156 hc->max_trans = poll << 1;
1157 if (hc->max_trans > hc->Zlen)
1158 hc->max_trans = hc->Zlen;
1161 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1164 __func__, hc->id + 1);
1166 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1190 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1200 __func__, plx_last_hc->id + 1);
1202 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1213 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1216 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1217 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1219 /* we only want the real Z2 read-pointer for revision > 0 */
1220 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1221 hc->hw.r_ram_sz |= V_FZ_MD;
1224 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1229 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1233 hc->hw.r_pcm_md0 |= V_PCM_MD;
1241 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1242 if (hc->ctype == HFC_TYPE_XHFC)
1246 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1248 if (hc->ctype == HFC_TYPE_XHFC)
1249 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1251 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1253 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1255 hc->hw.r_cirm = 0;
1256 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1258 if (hc->ctype != HFC_TYPE_XHFC)
1259 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1262 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1264 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1267 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1285 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1286 if (hc->slots == 32)
1288 if (hc->slots == 64)
1290 if (hc->slots == 128)
1292 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1293 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1295 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1299 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1303 if (hc->ctype != HFC_TYPE_XHFC)
1305 hc->slot_owner[i] = -1;
1309 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1316 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1320 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1335 spin_unlock_irqrestore(&hc->lock, flags);
1338 spin_lock_irqsave(&hc->lock, flags);
1347 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1350 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1353 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1359 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1363 err = -EIO;
1366 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1371 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1376 err = -EIO;
1380 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1382 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1392 hc->hw.r_pcm_md0 |= V_PCM_MD;
1393 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1394 spin_unlock_irqrestore(&hc->lock, flags);
1397 spin_lock_irqsave(&hc->lock, flags);
1405 &hc->chip);
1414 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1415 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1418 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1429 if (hc->pcm)
1431 hc->pcm);
1433 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1434 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1437 hc->pcm = PCM_cnt;
1439 "(auto selected)\n", hc->pcm);
1444 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1447 if (hc->ctype == HFC_TYPE_E1)
1448 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1451 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1454 "for all B-channel\n", __func__);
1455 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1456 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1457 hc->hw.r_dtmf |= V_ULAW_SEL;
1458 HFC_outb(hc, R_DTMF_N, 102 - 1);
1459 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1463 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1467 if (hc->ctype != HFC_TYPE_XHFC)
1471 switch (hc->leds) {
1472 case 1: /* HFC-E1 OEM */
1473 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1484 case 2: /* HFC-4S OEM */
1492 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1493 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1494 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1498 if (hc->masterclk >= 0) {
1502 __func__, hc->masterclk, hc->ports - 1);
1503 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1504 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1510 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1513 hc->hw.r_irqmsk_misc);
1535 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1536 err = -EIO;
1543 spin_unlock_irqrestore(&hc->lock, flags);
1554 hc->wdcount++;
1556 if (hc->wdcount > 10) {
1557 hc->wdcount = 0;
1558 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1561 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1563 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1581 switch (hc->leds) {
1582 case 1: /* HFC-E1 OEM */
1593 dch = hc->chan[hc->dnum[0]].dch;
1595 if (hc->chan[hc->dnum[0]].los)
1597 if (hc->e1_state != 1) {
1599 hc->flash[2] = 0;
1600 hc->flash[3] = 0;
1604 if (!hc->flash[2] && hc->activity_tx)
1605 hc->flash[2] = poll;
1606 if (!hc->flash[3] && hc->activity_rx)
1607 hc->flash[3] = poll;
1608 if (hc->flash[2] && hc->flash[2] < 1024)
1610 if (hc->flash[3] && hc->flash[3] < 1024)
1612 if (hc->flash[2] >= 2048)
1613 hc->flash[2] = 0;
1614 if (hc->flash[3] >= 2048)
1615 hc->flash[3] = 0;
1616 if (hc->flash[2])
1617 hc->flash[2] += poll;
1618 if (hc->flash[3])
1619 hc->flash[3] += poll;
1624 if (leds != (int)hc->ledstate) {
1626 hc->ledstate = leds;
1630 case 2: /* HFC-4S OEM */
1637 active = -1;
1638 dch = hc->chan[(i << 2) | 2].dch;
1640 state = dch->state;
1641 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1649 hc->activity_tx |= hc->activity_rx;
1650 if (!hc->flash[i] &&
1651 (hc->activity_tx & (1 << i)))
1652 hc->flash[i] = poll;
1653 if (hc->flash[i] && hc->flash[i] < 1024)
1655 if (hc->flash[i] >= 2048)
1656 hc->flash[i] = 0;
1657 if (hc->flash[i])
1658 hc->flash[i] += poll;
1661 hc->flash[i] = 0;
1666 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1677 if (leds != (int)hc->ledstate) {
1679 hc->ledstate = leds;
1686 if (leds != (int)hc->ledstate) {
1689 hc->ledstate = leds;
1701 active = -1;
1702 dch = hc->chan[(i << 2) | 2].dch;
1704 state = dch->state;
1705 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1713 hc->activity_tx |= hc->activity_rx;
1714 if (!hc->flash[i] &&
1715 (hc->activity_tx & (1 << i)))
1716 hc->flash[i] = poll;
1717 if (hc->flash[i] < 1024)
1719 if (hc->flash[i] >= 2048)
1720 hc->flash[i] = 0;
1721 if (hc->flash[i])
1722 hc->flash[i] += poll;
1725 hc->flash[i] = 0;
1732 if (leds != (int)hc->ledstate) {
1737 hc->ledstate = leds;
1748 active = -1;
1749 dch = hc->chan[(i << 2) | 2].dch;
1751 state = dch->state;
1752 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1760 hc->activity_tx |= hc->activity_rx;
1761 if (!hc->flash[i] &&
1762 (hc->activity_tx & (1 << i)))
1763 hc->flash[i] = poll;
1764 if (hc->flash[i] < 1024)
1766 if (hc->flash[i] >= 2048)
1767 hc->flash[i] = 0;
1768 if (hc->flash[i])
1769 hc->flash[i] += poll;
1771 hc->flash[i] = 0;
1775 if (leddw != hc->ledstate) {
1780 outw(0x4000, hc->pci_iobase + 4);
1781 outl(leddw, hc->pci_iobase);
1783 hc->ledstate = leddw;
1787 hc->activity_tx = 0;
1788 hc->activity_rx = 0;
1811 /* only process enabled B-channels */
1812 bch = hc->chan[ch].bch;
1815 if (!hc->created[hc->chan[ch].port])
1817 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1822 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1825 /* read W(n-1) coefficient */
1826 addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1843 mantissa <<= (exponent - 1);
1862 mantissa <<= (exponent - 1);
1873 hc->chan[ch].coeff_count++;
1874 if (hc->chan[ch].coeff_count == 8) {
1875 hc->chan[ch].coeff_count = 0;
1883 hh->prim = PH_CONTROL_IND;
1884 hh->id = DTMF_HFC_COEF;
1885 skb_put_data(skb, hc->chan[ch].coeff, 512);
1891 hc->dtmf = dtmf;
1893 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1911 struct sk_buff **sp = NULL;
1914 bch = hc->chan[ch].bch;
1915 dch = hc->chan[ch].dch;
1919 txpending = &hc->chan[ch].txpending;
1920 slot_tx = hc->chan[ch].slot_tx;
1922 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1924 sp = &dch->tx_skb;
1925 idxp = &dch->tx_idx;
1927 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1929 sp = &bch->tx_skb;
1930 idxp = &bch->tx_idx;
1932 if (*sp)
1933 len = (*sp)->len;
1938 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1939 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1940 (hc->chan[ch].slot_rx < 0) &&
1941 (hc->chan[ch].slot_tx < 0))
1955 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1962 __func__, hc->id + 1, temp, f2);
1965 Fspace = f2 - f1 - 1;
1967 Fspace += hc->Flen;
1974 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1980 /* one frame only for ST D-channels, to allow resending */
1981 if (hc->ctype != HFC_TYPE_E1 && dch) {
1985 /* F-counter full condition */
1989 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1990 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1991 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1994 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1997 hc->chan[ch].Zfill = z1 - z2;
1998 if (hc->chan[ch].Zfill < 0)
1999 hc->chan[ch].Zfill += hc->Zlen;
2000 Zspace = z2 - z1;
2002 Zspace += hc->Zlen;
2003 Zspace -= 4; /* keep not too full, so pointers will not overrun */
2005 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2006 Zspace = Zspace - hc->Zlen + hc->max_trans;
2014 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2023 if (hc->ctype == HFC_TYPE_XHFC)
2032 if (hc->ctype == HFC_TYPE_XHFC)
2048 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2049 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2054 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2055 Zspace -= (poll >> 1);
2059 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2066 if (hc->ctype == HFC_TYPE_XHFC)
2075 if (hc->ctype == HFC_TYPE_XHFC)
2089 hc->activity_tx |= 1 << hc->chan[ch].port;
2093 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2098 d = (*sp)->data + i;
2099 if (ii - i > Zspace)
2104 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2108 hc->write_fifo(hc, d, ii - i);
2109 hc->chan[ch].Zfill += ii - i;
2119 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2120 /* increment f-counter */
2125 tmp_len = (*sp)->len;
2126 dev_kfree_skb(*sp);
2142 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2143 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2157 struct sk_buff *skb, **sp = NULL;
2160 bch = hc->chan[ch].bch;
2162 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2164 } else if (hc->chan[ch].dch) {
2165 dch = hc->chan[ch].dch;
2166 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2174 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2175 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2176 (hc->chan[ch].slot_rx < 0) &&
2177 (hc->chan[ch].slot_tx < 0))
2184 if (hc->chan[ch].rx_off) {
2186 bch->dropcnt += poll; /* not exact but fair enough */
2190 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2196 __func__, hc->id + 1, temp, f1);
2201 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2202 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2205 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2208 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2209 Zsize = z1 - z2;
2210 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2214 Zsize += hc->Zlen;
2223 hc->id + 1, bch->nr, Zsize);
2226 sp = &bch->rx_skb;
2227 maxlen = bch->maxlen;
2229 sp = &dch->rx_skb;
2230 maxlen = dch->maxlen + 3;
2231 if (*sp == NULL) {
2232 *sp = mI_alloc_skb(maxlen, GFP_ATOMIC);
2233 if (*sp == NULL) {
2235 hc->id + 1);
2242 hc->activity_rx |= 1 << hc->chan[ch].port;
2245 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2249 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2251 f1, f2, Zsize + (*sp)->len, again);
2253 if ((Zsize + (*sp)->len) > maxlen) {
2256 "%s(card %d): hdlc-frame too large.\n",
2257 __func__, hc->id + 1);
2258 skb_trim(*sp, 0);
2264 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2267 /* increment Z2,F2-counter */
2271 if ((*sp)->len < 4) {
2275 "size\n", __func__, hc->id + 1);
2276 skb_trim(*sp, 0);
2280 if ((*sp)->data[(*sp)->len - 1]) {
2283 "%s: CRC-error\n", __func__);
2284 skb_trim(*sp, 0);
2287 skb_trim(*sp, (*sp)->len - 3);
2288 if ((*sp)->len < MISDN_COPY_SIZE) {
2289 skb = *sp;
2290 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2291 if (*sp) {
2292 skb_put_data(*sp, skb->data, skb->len);
2297 *sp = skb;
2305 __func__, hc->id + 1);
2307 while (temp < (*sp)->len)
2308 printk(" %02x", (*sp)->data[temp++]);
2315 *sp = skb;
2322 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2327 __func__, hc->id + 1, ch, Zsize, z1, z2);
2329 recv_Bchannel(bch, hc->chan[ch].Zfill, false);
2363 if (hc->e1_resync) {
2366 if (hc->e1_resync & 1) {
2371 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2374 if (hc->e1_resync & 2) {
2379 if (hc->e1_resync & 4) {
2382 "Enable QUARTZ for HFC-E1\n");
2389 hc->e1_resync = 0;
2393 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2395 if (hc->created[hc->chan[ch].port]) {
2397 /* fifo is started when switching to rx-fifo */
2399 if (hc->chan[ch].dch &&
2400 hc->chan[ch].nt_timer > -1) {
2401 dch = hc->chan[ch].dch;
2402 if (!(--hc->chan[ch].nt_timer)) {
2411 dch->state);
2416 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2417 dch = hc->chan[hc->dnum[0]].dch;
2420 hc->chan[hc->dnum[0]].los = temp;
2421 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2422 if (!temp && hc->chan[hc->dnum[0]].los)
2425 if (temp && !hc->chan[hc->dnum[0]].los)
2429 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
2432 if (!temp && hc->chan[hc->dnum[0]].ais)
2435 if (temp && !hc->chan[hc->dnum[0]].ais)
2438 hc->chan[hc->dnum[0]].ais = temp;
2440 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
2443 if (!temp && hc->chan[hc->dnum[0]].slip_rx)
2446 hc->chan[hc->dnum[0]].slip_rx = temp;
2448 if (!temp && hc->chan[hc->dnum[0]].slip_tx)
2451 hc->chan[hc->dnum[0]].slip_tx = temp;
2453 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
2456 if (!temp && hc->chan[hc->dnum[0]].rdi)
2459 if (temp && !hc->chan[hc->dnum[0]].rdi)
2462 hc->chan[hc->dnum[0]].rdi = temp;
2465 switch (hc->chan[hc->dnum[0]].sync) {
2472 __func__, hc->id);
2474 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2476 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2477 hc->chan[hc->dnum[0]].sync = 1;
2487 __func__, hc->id);
2488 hc->chan[hc->dnum[0]].sync = 0;
2498 __func__, hc->id);
2499 hc->chan[hc->dnum[0]].sync = 2;
2508 __func__, hc->id);
2509 hc->chan[hc->dnum[0]].sync = 0;
2518 __func__, hc->id);
2519 hc->chan[hc->dnum[0]].sync = 1;
2525 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2528 if (hc->leds)
2542 if (hc->chan[ch].dch) {
2543 dch = hc->chan[ch].dch;
2546 hc->chan[ch].port);
2561 /* Speech Design TE-sync indication */
2562 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2563 dch->dev.D.protocol == ISDN_P_TE_S0) {
2565 hc->syncronized |=
2566 (1 << hc->chan[ch].port);
2568 hc->syncronized &=
2569 ~(1 << hc->chan[ch].port);
2571 dch->state = st_status & 0x0f;
2572 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2576 if (dch->state == active) {
2583 dch->tx_idx = 0;
2589 __func__, dch->state,
2590 hc->chan[ch].port);
2595 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2611 dch = hc->chan[ch].dch;
2612 bch = hc->chan[ch].bch;
2613 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2618 test_bit(FLG_ACTIVE, &dch->Flags)) {
2625 test_bit(FLG_ACTIVE, &bch->Flags)) {
2633 test_bit(FLG_ACTIVE, &dch->Flags)) {
2637 test_bit(FLG_ACTIVE, &bch->Flags)) {
2664 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2668 spin_lock(&hc->lock);
2673 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2674 irqsem = hc->id + 1;
2677 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2680 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2682 plx_acc = hc->plx_membase + PLX_INTCSR;
2717 hc->irqcnt++;
2719 if (hc->ctype != HFC_TYPE_E1)
2729 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2731 if (hc->ctype == HFC_TYPE_E1) {
2733 dch = hc->chan[hc->dnum[0]].dch;
2735 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2736 && hc->e1_getclock) {
2738 hc->syncronized = 1;
2740 hc->syncronized = 0;
2756 __func__, hc->id, temp & 0x7);
2757 for (i = 0; i < hc->ports; i++) {
2758 dch = hc->chan[hc->dnum[i]].dch;
2759 dch->state = temp & 0x7;
2763 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2768 if (hc->iclock_on)
2769 mISDN_clock_update(hc->iclock, poll, NULL);
2779 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2796 spin_unlock(&hc->lock);
2803 spin_unlock(&hc->lock);
2809 * timer callback for D-chan busy resolution. Currently no function
2821 * configure B-channel with the given protocol
2822 * ch eqals to the HFC-channel (0-31)
2823 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2824 * for S/T, 1-31 for E1)
2836 return -EINVAL;
2837 oslot_tx = hc->chan[ch].slot_tx;
2838 oslot_rx = hc->chan[ch].slot_rx;
2839 conf = hc->chan[ch].conf;
2845 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2853 if (hc->slot_owner[oslot_tx << 1] == ch) {
2856 if (hc->ctype != HFC_TYPE_XHFC)
2858 hc->slot_owner[oslot_tx << 1] = -1;
2864 __func__, hc->slot_owner[oslot_tx << 1]);
2874 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2877 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2884 hc->slot_owner[(oslot_rx << 1) | 1]);
2889 flow_tx = 0x80; /* FIFO->ST */
2891 hc->chan[ch].slot_tx = -1;
2892 hc->chan[ch].bank_tx = 0;
2895 if (hc->chan[ch].txpending)
2896 flow_tx = 0x80; /* FIFO->ST */
2898 flow_tx = 0xc0; /* PCM->ST */
2910 if (hc->ctype != HFC_TYPE_XHFC)
2913 hc->slot_owner[slot_tx << 1] = ch;
2914 hc->chan[ch].slot_tx = slot_tx;
2915 hc->chan[ch].bank_tx = bank_tx;
2919 flow_rx = 0x80; /* ST->FIFO */
2920 hc->chan[ch].slot_rx = -1;
2921 hc->chan[ch].bank_rx = 0;
2924 if (hc->chan[ch].txpending)
2925 flow_rx = 0x80; /* ST->FIFO */
2927 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2939 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2940 hc->chan[ch].slot_rx = slot_rx;
2941 hc->chan[ch].bank_rx = bank_rx;
2962 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2963 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2965 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2969 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2971 if (hc->chan[ch].bch) {
2972 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2974 &hc->chan[ch].bch->Flags);
2977 case (ISDN_P_B_RAW): /* B-channel */
2979 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2980 (hc->chan[ch].slot_rx < 0) &&
2981 (hc->chan[ch].slot_tx < 0)) {
2984 "Setting B-channel %d to echo cancelable "
2992 /* S/T -> PCM */
3000 /* PCM -> FIFO */
3006 if (hc->chan[ch].protocol != protocol) {
3015 /* PCM -> S/T */
3023 /* FIFO -> PCM */
3029 if (hc->chan[ch].protocol != protocol) {
3034 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3042 if (hc->ctype == HFC_TYPE_XHFC)
3051 if (hc->chan[ch].protocol != protocol) {
3056 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3060 if (hc->ctype == HFC_TYPE_XHFC)
3069 if (hc->chan[ch].protocol != protocol) {
3074 if (hc->ctype != HFC_TYPE_E1) {
3075 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3077 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3081 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3083 if (hc->chan[ch].bch)
3085 &hc->chan[ch].bch->Flags);
3087 case (ISDN_P_B_HDLC): /* B-channel */
3088 case (ISDN_P_TE_S0): /* D-channel */
3095 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3096 /* E1 or B-channel */
3100 /* D-Channel without HDLC fill flags */
3111 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3118 if (hc->chan[ch].bch) {
3119 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3120 if (hc->ctype != HFC_TYPE_E1) {
3121 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3123 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3127 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3134 hc->chan[ch].protocol = ISDN_P_NONE;
3135 return -ENOPROTOOPT;
3137 hc->chan[ch].protocol = protocol;
3152 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3157 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3169 hc->chan[ch].conf = num;
3171 hc->chan[ch].conf = -1;
3172 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3173 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3174 hc->chan[ch].bank_rx);
3182 /* NOTE: this function is experimental and therefore disabled */
3190 struct hfc_multi *hc = dch->hw;
3200 spin_lock_irqsave(&hc->lock, flags);
3201 if (hc->ctype == HFC_TYPE_E1) {
3207 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3216 spin_unlock_irqrestore(&hc->lock, flags);
3217 l1_event(dch->l1, HW_POWERUP_IND);
3222 spin_lock_irqsave(&hc->lock, flags);
3223 if (hc->ctype == HFC_TYPE_E1) {
3229 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3234 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3235 hc->syncronized &=
3236 ~(1 << hc->chan[dch->slot].port);
3240 skb_queue_splice_init(&dch->squeue, &free_queue);
3241 if (dch->tx_skb) {
3242 __skb_queue_tail(&free_queue, dch->tx_skb);
3243 dch->tx_skb = NULL;
3245 dch->tx_idx = 0;
3246 if (dch->rx_skb) {
3247 __skb_queue_tail(&free_queue, dch->rx_skb);
3248 dch->rx_skb = NULL;
3250 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3251 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3252 timer_delete(&dch->timer);
3253 spin_unlock_irqrestore(&hc->lock, flags);
3257 spin_lock_irqsave(&hc->lock, flags);
3258 if (hc->ctype == HFC_TYPE_E1) {
3264 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3271 spin_unlock_irqrestore(&hc->lock, flags);
3274 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3275 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3279 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3280 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3284 if (dch->debug & DEBUG_HW)
3287 return -1;
3293 * Layer2 -> Layer 1 Transfer
3301 struct hfc_multi *hc = dch->hw;
3303 int ret = -EINVAL;
3307 switch (hh->prim) {
3309 if (skb->len < 1)
3311 spin_lock_irqsave(&hc->lock, flags);
3314 id = hh->id; /* skb can be freed */
3315 hfcmulti_tx(hc, dch->slot);
3320 spin_unlock_irqrestore(&hc->lock, flags);
3323 spin_unlock_irqrestore(&hc->lock, flags);
3326 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3327 spin_lock_irqsave(&hc->lock, flags);
3332 __func__, hc->chan[dch->slot].port,
3333 hc->ports - 1);
3335 if (hc->ctype == HFC_TYPE_E1) {
3340 __func__, dch->state);
3343 hc->chan[dch->slot].port);
3352 dch->state = 1;
3354 spin_unlock_irqrestore(&hc->lock, flags);
3356 ret = l1_event(dch->l1, hh->prim);
3359 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3360 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3364 spin_lock_irqsave(&hc->lock, flags);
3368 __func__, hc->chan[dch->slot].port,
3369 hc->ports - 1);
3371 if (hc->ctype == HFC_TYPE_E1) {
3378 hc->chan[dch->slot].port);
3383 dch->state = 1;
3385 skb_queue_splice_init(&dch->squeue, &free_queue);
3386 if (dch->tx_skb) {
3387 __skb_queue_tail(&free_queue, dch->tx_skb);
3388 dch->tx_skb = NULL;
3390 dch->tx_idx = 0;
3391 if (dch->rx_skb) {
3392 __skb_queue_tail(&free_queue, dch->rx_skb);
3393 dch->rx_skb = NULL;
3395 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3396 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3397 timer_delete(&dch->timer);
3399 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3400 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3403 spin_unlock_irqrestore(&hc->lock, flags);
3406 ret = l1_event(dch->l1, hh->prim);
3417 struct hfc_multi *hc = bch->hw;
3420 spin_lock_irqsave(&hc->lock, flags);
3422 hc->chan[bch->slot].coeff_count = 0;
3423 hc->chan[bch->slot].rx_off = 0;
3424 hc->chan[bch->slot].conf = -1;
3425 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3426 spin_unlock_irqrestore(&hc->lock, flags);
3433 struct hfc_multi *hc = bch->hw;
3434 int ret = -EINVAL;
3438 switch (hh->prim) {
3440 if (!skb->len)
3442 spin_lock_irqsave(&hc->lock, flags);
3445 hfcmulti_tx(hc, bch->slot);
3451 spin_unlock_irqrestore(&hc->lock, flags);
3456 __func__, bch->slot);
3457 spin_lock_irqsave(&hc->lock, flags);
3458 /* activate B-channel if not already activated */
3459 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3460 hc->chan[bch->slot].txpending = 0;
3461 ret = mode_hfcmulti(hc, bch->slot,
3462 ch->protocol,
3463 hc->chan[bch->slot].slot_tx,
3464 hc->chan[bch->slot].bank_tx,
3465 hc->chan[bch->slot].slot_rx,
3466 hc->chan[bch->slot].bank_rx);
3468 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3469 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3471 hc->dtmf = 1;
3476 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3482 spin_unlock_irqrestore(&hc->lock, flags);
3488 spin_lock_irqsave(&hc->lock, flags);
3489 switch (hh->id) {
3494 __func__, skb->len);
3506 __func__, hh->id);
3507 ret = -EINVAL;
3509 spin_unlock_irqrestore(&hc->lock, flags);
3531 (struct dsp_features *)(*((u_long *)&cq->p1));
3532 struct hfc_multi *hc = bch->hw;
3539 switch (cq->op) {
3542 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
3546 hc->chan[bch->slot].rx_off = !!cq->p1;
3547 if (!hc->chan[bch->slot].rx_off) {
3549 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3556 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3560 hc->silence = bch->fill[0];
3561 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
3568 features->hfc_id = hc->id;
3569 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3570 features->hfc_dtmf = 1;
3571 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3572 features->hfc_conf = 1;
3573 features->hfc_loops = 0;
3574 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3575 features->hfc_echocanhw = 1;
3577 features->pcm_id = hc->pcm;
3578 features->pcm_slots = hc->slots;
3579 features->pcm_banks = 2;
3583 slot_tx = cq->p1 & 0xff;
3584 bank_tx = cq->p1 >> 8;
3585 slot_rx = cq->p2 & 0xff;
3586 bank_rx = cq->p2 >> 8;
3593 if (slot_tx < hc->slots && bank_tx <= 2 &&
3594 slot_rx < hc->slots && bank_rx <= 2)
3595 hfcmulti_pcm(hc, bch->slot,
3603 ret = -EINVAL;
3610 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3613 num = cq->p1 & 0xff;
3618 hfcmulti_conf(hc, bch->slot, num);
3623 ret = -EINVAL;
3629 hfcmulti_conf(hc, bch->slot, -1);
3634 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3635 vpm_echocan_on(hc, bch->slot, cq->p1);
3637 ret = -EINVAL;
3644 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3645 vpm_echocan_off(hc, bch->slot);
3647 ret = -EINVAL;
3660 struct hfc_multi *hc = bch->hw;
3661 int err = -EINVAL;
3664 if (bch->debug & DEBUG_HW)
3669 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3671 ch->protocol = ISDN_P_NONE;
3672 ch->peer = NULL;
3677 spin_lock_irqsave(&hc->lock, flags);
3679 spin_unlock_irqrestore(&hc->lock, flags);
3689 * handle D-channel events
3703 hc = dch->hw;
3704 ch = dch->slot;
3706 if (hc->ctype == HFC_TYPE_E1) {
3707 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3711 __func__, hc->id, dch->state);
3716 __func__, hc->id, dch->state);
3718 switch (dch->state) {
3720 if (hc->e1_state != 1) {
3731 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3732 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3737 if (hc->e1_state != 1)
3739 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3740 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3743 hc->e1_state = dch->state;
3745 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3749 __func__, dch->state);
3750 switch (dch->state) {
3752 l1_event(dch->l1, HW_RESET_IND);
3755 l1_event(dch->l1, HW_DEACT_IND);
3759 l1_event(dch->l1, ANYSIGNAL);
3762 l1_event(dch->l1, INFO2);
3765 l1_event(dch->l1, INFO4_P8);
3771 __func__, dch->state);
3772 switch (dch->state) {
3774 if (hc->chan[ch].nt_timer == 0) {
3775 hc->chan[ch].nt_timer = -1;
3777 hc->chan[ch].port);
3784 dch->state = 4;
3787 hc->chan[ch].nt_timer =
3790 hc->chan[ch].port);
3793 /* allow G2 -> G3 transition */
3799 hc->chan[ch].nt_timer = -1;
3800 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3801 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3805 hc->chan[ch].nt_timer = -1;
3808 hc->chan[ch].nt_timer = -1;
3809 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3810 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3825 struct hfc_multi *hc = dch->hw;
3832 i = dch->slot;
3833 pt = hc->chan[i].port;
3834 if (hc->ctype == HFC_TYPE_E1) {
3836 hc->chan[hc->dnum[pt]].slot_tx = -1;
3837 hc->chan[hc->dnum[pt]].slot_rx = -1;
3838 hc->chan[hc->dnum[pt]].conf = -1;
3839 if (hc->dnum[pt]) {
3840 mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol,
3841 -1, 0, -1, 0);
3842 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3845 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
3847 hc->chan[i].slot_tx = -1;
3848 hc->chan[i].slot_rx = -1;
3849 hc->chan[i].conf = -1;
3850 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3853 if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3855 dch = hc->chan[hc->dnum[0]].dch;
3856 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
3860 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
3862 hc->hw.r_tx0 = 0 | V_OUT_EN;
3865 hc->hw.r_tx0 = 1 | V_OUT_EN;
3867 hc->hw.r_tx1 = V_ATX | V_NTRI;
3868 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3869 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3873 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3878 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3881 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3883 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3886 hc->e1_getclock = 0;
3889 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3892 hc->e1_getclock = 1;
3894 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3898 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3899 hc->e1_getclock = 1;
3900 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3901 hc->e1_getclock = 0;
3902 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3910 if (hc->e1_getclock) {
3937 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3938 hc->syncronized = 0;
3942 if (hc->ctype != HFC_TYPE_E1) {
3944 hc->chan[i].slot_tx = -1;
3945 hc->chan[i].slot_rx = -1;
3946 hc->chan[i].conf = -1;
3947 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3948 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3949 hc->chan[i - 2].slot_tx = -1;
3950 hc->chan[i - 2].slot_rx = -1;
3951 hc->chan[i - 2].conf = -1;
3952 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3953 hc->chan[i - 1].slot_tx = -1;
3954 hc->chan[i - 1].slot_rx = -1;
3955 hc->chan[i - 1].conf = -1;
3956 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3961 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3964 "%s: ST port %d is NT-mode\n",
3969 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3973 "%s: ST port %d is TE-mode\n",
3978 hc->hw.a_st_ctrl0[pt] = 0;
3980 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3981 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3982 if (hc->ctype == HFC_TYPE_XHFC) {
3983 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
3988 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
3989 /* disable E-channel */
3990 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3991 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3995 /* enable B-channel receive */
4001 hc->hw.r_sci_msk |= 1 << pt;
4003 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4005 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4006 hc->syncronized &=
4007 ~(1 << hc->chan[dch->slot].port);
4025 dch->dev.id, __builtin_return_address(0));
4026 if (rq->protocol == ISDN_P_NONE)
4027 return -EINVAL;
4028 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4029 (dch->dev.D.protocol != rq->protocol)) {
4032 __func__, dch->dev.D.protocol, rq->protocol);
4034 if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4035 (rq->protocol != ISDN_P_TE_S0))
4036 l1_event(dch->l1, CLOSE_CHANNEL);
4037 if (dch->dev.D.protocol != rq->protocol) {
4038 if (rq->protocol == ISDN_P_TE_S0) {
4043 dch->dev.D.protocol = rq->protocol;
4044 spin_lock_irqsave(&hc->lock, flags);
4046 spin_unlock_irqrestore(&hc->lock, flags);
4048 if (test_bit(FLG_ACTIVE, &dch->Flags))
4049 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4051 rq->ch = &dch->dev.D;
4064 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4065 return -EINVAL;
4066 if (rq->protocol == ISDN_P_NONE)
4067 return -EINVAL;
4068 if (hc->ctype == HFC_TYPE_E1)
4069 ch = rq->adr.channel;
4071 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4072 bch = hc->chan[ch].bch;
4076 return -EINVAL;
4078 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4079 return -EBUSY; /* b-channel can be only open once */
4080 bch->ch.protocol = rq->protocol;
4081 hc->chan[ch].rx_off = 0;
4082 rq->ch = &bch->ch;
4094 struct hfc_multi *hc = dch->hw;
4098 switch (cq->op) {
4100 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
4103 wd_cnt = cq->p1 & 0xf;
4104 wd_mode = !!(cq->p1 >> 4);
4111 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4112 if (hc->ctype == HFC_TYPE_XHFC)
4113 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4115 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4116 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4117 /* enable the watchdog output for Speech-Design */
4128 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4131 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4135 __func__, cq->op);
4136 ret = -EINVAL;
4147 struct hfc_multi *hc = dch->hw;
4152 if (dch->debug & DEBUG_HW)
4158 switch (rq->protocol) {
4161 if (hc->ctype == HFC_TYPE_E1) {
4162 err = -EINVAL;
4169 if (hc->ctype != HFC_TYPE_E1) {
4170 err = -EINVAL;
4176 spin_lock_irqsave(&hc->lock, flags);
4178 spin_unlock_irqrestore(&hc->lock, flags);
4184 __func__, dch->dev.id,
4189 spin_lock_irqsave(&hc->lock, flags);
4191 spin_unlock_irqrestore(&hc->lock, flags);
4194 if (dch->debug & DEBUG_HW)
4197 err = -EINVAL;
4207 hc->iclock_on = enable;
4222 int err = -EIO;
4230 spin_lock_irqsave(&hc->lock, flags);
4231 /* set interrupts but leave global interrupt disabled */
4232 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4234 spin_unlock_irqrestore(&hc->lock, flags);
4236 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4237 "HFC-multi", hc)) {
4239 hc->irq);
4240 hc->irq = 0;
4241 return -EIO;
4244 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4246 plx_acc = hc->plx_membase + PLX_INTCSR;
4254 __func__, hc->irq, hc->irqcnt);
4263 spin_lock_irqsave(&hc->lock, flags);
4265 spin_unlock_irqrestore(&hc->lock, flags);
4270 spin_lock_irqsave(&hc->lock, flags);
4272 spin_unlock_irqrestore(&hc->lock, flags);
4275 __func__, hc->irq, hc->irqcnt);
4276 if (hc->irqcnt) {
4282 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4288 hc->irq);
4290 err = -EIO;
4293 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4295 plx_acc = hc->plx_membase + PLX_INTCSR;
4301 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4302 if (hc->irq) {
4303 free_irq(hc->irq, hc);
4304 hc->irq = 0;
4320 struct hm_map *m = (struct hm_map *)ent->driver_data;
4323 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4324 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4326 hc->pci_dev = pdev;
4327 if (m->clock2)
4328 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4330 if (ent->vendor == PCI_VENDOR_ID_DIGIUM &&
4331 ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) {
4332 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4333 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4334 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4335 hc->slots = 32;
4338 if (hc->pci_dev->irq <= 0) {
4339 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4340 return -EIO;
4342 if (pci_enable_device(hc->pci_dev)) {
4343 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4344 return -EIO;
4346 hc->leds = m->leds;
4347 hc->ledstate = 0xAFFEAFFE;
4348 hc->opticalsupport = m->opticalsupport;
4350 hc->pci_iobase = 0;
4351 hc->pci_membase = NULL;
4352 hc->plx_membase = NULL;
4355 if (m->io_mode) /* use mode from card config */
4356 hc->io_mode = m->io_mode;
4357 switch (hc->io_mode) {
4359 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4360 hc->slots = 128; /* required */
4361 hc->HFC_outb = HFC_outb_pcimem;
4362 hc->HFC_inb = HFC_inb_pcimem;
4363 hc->HFC_inw = HFC_inw_pcimem;
4364 hc->HFC_wait = HFC_wait_pcimem;
4365 hc->read_fifo = read_fifo_pcimem;
4366 hc->write_fifo = write_fifo_pcimem;
4367 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4370 if (!hc->plx_origmembase) {
4372 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4373 pci_disable_device(hc->pci_dev);
4374 return -EIO;
4377 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4378 if (!hc->plx_membase) {
4380 "HFC-multi: failed to remap plx address space. "
4382 pci_disable_device(hc->pci_dev);
4383 return -EIO;
4386 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4387 (u_long)hc->plx_membase, hc->plx_origmembase);
4389 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4391 if (!hc->pci_origmembase) {
4393 "HFC-multi: No IO-Memory for PCI card found\n");
4394 pci_disable_device(hc->pci_dev);
4395 return -EIO;
4398 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4399 if (!hc->pci_membase) {
4400 printk(KERN_WARNING "HFC-multi: failed to remap io "
4402 pci_disable_device(hc->pci_dev);
4403 return -EIO;
4408 "leds-type %d\n",
4409 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4410 hc->pci_dev->irq, HZ, hc->leds);
4411 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4414 hc->HFC_outb = HFC_outb_pcimem;
4415 hc->HFC_inb = HFC_inb_pcimem;
4416 hc->HFC_inw = HFC_inw_pcimem;
4417 hc->HFC_wait = HFC_wait_pcimem;
4418 hc->read_fifo = read_fifo_pcimem;
4419 hc->write_fifo = write_fifo_pcimem;
4420 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4421 if (!hc->pci_origmembase) {
4423 "HFC-multi: No IO-Memory for PCI card found\n");
4424 pci_disable_device(hc->pci_dev);
4425 return -EIO;
4428 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4429 if (!hc->pci_membase) {
4431 "HFC-multi: failed to remap io address space. "
4433 pci_disable_device(hc->pci_dev);
4434 return -EIO;
4437 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4438 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4439 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4442 hc->HFC_outb = HFC_outb_regio;
4443 hc->HFC_inb = HFC_inb_regio;
4444 hc->HFC_inw = HFC_inw_regio;
4445 hc->HFC_wait = HFC_wait_regio;
4446 hc->read_fifo = read_fifo_regio;
4447 hc->write_fifo = write_fifo_regio;
4448 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4449 if (!hc->pci_iobase) {
4451 "HFC-multi: No IO for PCI card found\n");
4452 pci_disable_device(hc->pci_dev);
4453 return -EIO;
4456 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4457 printk(KERN_WARNING "HFC-multi: failed to request "
4459 hc->pci_iobase);
4460 pci_disable_device(hc->pci_dev);
4461 return -EIO;
4465 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4466 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4467 hc->pci_dev->irq, HZ, hc->leds);
4468 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4471 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4472 pci_disable_device(hc->pci_dev);
4473 return -EIO;
4476 pci_set_drvdata(hc->pci_dev, hc);
4495 ci = dch->slot;
4496 pt = hc->chan[ci].port;
4502 if (pt >= hc->ports) {
4512 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4513 l1_event(dch->l1, CLOSE_CHANNEL);
4515 hc->chan[ci].dch = NULL;
4517 if (hc->created[pt]) {
4518 hc->created[pt] = 0;
4519 mISDN_unregister_device(&dch->dev);
4522 spin_lock_irqsave(&hc->lock, flags);
4524 if (dch->timer.function) {
4525 timer_delete(&dch->timer);
4526 dch->timer.function = NULL;
4529 if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4531 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4532 hc->syncronized = 0;
4537 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4539 if (hc->chan[i].bch) {
4543 __func__, hc->chan[i].port + 1, i);
4544 pb = hc->chan[i].bch;
4545 hc->chan[i].bch = NULL;
4546 spin_unlock_irqrestore(&hc->lock, flags);
4549 kfree(hc->chan[i].coeff);
4550 spin_lock_irqsave(&hc->lock, flags);
4555 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4556 hc->syncronized &=
4557 ~(1 << hc->chan[ci].port);
4561 if (hc->chan[ci - 2].bch) {
4565 __func__, hc->chan[ci - 2].port + 1,
4566 ci - 2);
4567 pb = hc->chan[ci - 2].bch;
4568 hc->chan[ci - 2].bch = NULL;
4569 spin_unlock_irqrestore(&hc->lock, flags);
4572 kfree(hc->chan[ci - 2].coeff);
4573 spin_lock_irqsave(&hc->lock, flags);
4575 if (hc->chan[ci - 1].bch) {
4579 __func__, hc->chan[ci - 1].port + 1,
4580 ci - 1);
4581 pb = hc->chan[ci - 1].bch;
4582 hc->chan[ci - 1].bch = NULL;
4583 spin_unlock_irqrestore(&hc->lock, flags);
4586 kfree(hc->chan[ci - 1].coeff);
4587 spin_lock_irqsave(&hc->lock, flags);
4591 spin_unlock_irqrestore(&hc->lock, flags);
4611 __func__, hc->id);
4614 if (hc->iclock)
4615 mISDN_unregister_clock(hc->iclock);
4618 spin_lock_irqsave(&hc->lock, flags);
4620 spin_unlock_irqrestore(&hc->lock, flags);
4622 if (hc->irq) {
4625 __func__, hc->irq, hc);
4626 free_irq(hc->irq, hc);
4627 hc->irq = 0;
4631 /* disable D-channels & B-channels */
4636 if (hc->chan[ch].dch)
4637 release_port(hc, hc->chan[ch].dch);
4641 if (hc->leds)
4650 list_del(&hc->list);
4667 if (!m->opticalsupport) {
4680 &hc->chan[hc->dnum[0]].cfg);
4690 &hc->chan[hc->dnum[0]].cfg);
4699 &hc->chan[hc->dnum[0]].cfg);
4709 &hc->chan[hc->dnum[0]].cfg);
4719 &hc->chan[hc->dnum[0]].cfg);
4721 /* set CRC-4 Mode */
4728 &hc->chan[hc->dnum[0]].cfg);
4741 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4748 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4756 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4760 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
4765 __func__, hc->chan[hc->dnum[0]].jitter,
4768 hc->chan[hc->dnum[0]].jitter = 2; /* default */
4782 return -ENOMEM;
4783 dch->debug = debug;
4785 dch->hw = hc;
4786 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4787 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4789 dch->dev.D.send = handle_dmsg;
4790 dch->dev.D.ctrl = hfcm_dctrl;
4791 dch->slot = hc->dnum[pt];
4792 hc->chan[hc->dnum[pt]].dch = dch;
4793 hc->chan[hc->dnum[pt]].port = pt;
4794 hc->chan[hc->dnum[pt]].nt_timer = -1;
4796 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4802 ret = -ENOMEM;
4805 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4806 if (!hc->chan[ch].coeff) {
4809 ret = -ENOMEM;
4813 bch->nr = ch;
4814 bch->slot = ch;
4815 bch->debug = debug;
4817 bch->hw = hc;
4818 bch->ch.send = handle_bmsg;
4819 bch->ch.ctrl = hfcm_bctrl;
4820 bch->ch.nr = ch;
4821 list_add(&bch->ch.list, &dch->dev.bchannels);
4822 hc->chan[ch].bch = bch;
4823 hc->chan[ch].port = pt;
4824 set_channelmap(bch->nr, dch->dev.channelmap);
4827 dch->dev.nrbchan = bcount;
4830 if (hc->ports > 1)
4831 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d",
4834 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4835 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4838 hc->created[pt] = 1;
4855 return -ENOMEM;
4856 dch->debug = debug;
4858 dch->hw = hc;
4859 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4860 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4862 dch->dev.D.send = handle_dmsg;
4863 dch->dev.D.ctrl = hfcm_dctrl;
4864 dch->dev.nrbchan = 2;
4866 dch->slot = i + 2;
4867 hc->chan[i + 2].dch = dch;
4868 hc->chan[i + 2].port = pt;
4869 hc->chan[i + 2].nt_timer = -1;
4870 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4875 ret = -ENOMEM;
4878 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4879 if (!hc->chan[i + ch].coeff) {
4882 ret = -ENOMEM;
4886 bch->nr = ch + 1;
4887 bch->slot = i + ch;
4888 bch->debug = debug;
4890 bch->hw = hc;
4891 bch->ch.send = handle_bmsg;
4892 bch->ch.ctrl = hfcm_bctrl;
4893 bch->ch.nr = ch + 1;
4894 list_add(&bch->ch.list, &dch->dev.bchannels);
4895 hc->chan[i + ch].bch = bch;
4896 hc->chan[i + ch].port = pt;
4897 set_channelmap(bch->nr, dch->dev.channelmap);
4906 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4909 " possible with TE-mode\n",
4911 ret = -EINVAL;
4914 if (hc->masterclk >= 0) {
4918 pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4919 ret = -EINVAL;
4922 hc->masterclk = pt;
4932 &hc->chan[i + 2].cfg);
4934 /* disable E-channel */
4938 "%s: PROTOCOL disable E-channel: "
4942 &hc->chan[i + 2].cfg);
4944 if (hc->ctype == HFC_TYPE_XHFC) {
4945 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4947 ret = mISDN_register_device(&dch->dev, NULL, name);
4949 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4950 hc->ctype, HFC_cnt + 1, pt + 1);
4951 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4955 hc->created[pt] = 1;
4977 return -EINVAL;
4979 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4980 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4982 m->vendor_name, m->card_name, m->type, HFC_cnt,
4984 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4986 return -EINVAL;
4990 __func__, m->vendor_name, m->card_name, m->type,
4996 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4997 return -ENOMEM;
4999 spin_lock_init(&hc->lock);
5000 hc->mtyp = m;
5001 hc->ctype = m->type;
5002 hc->ports = m->ports;
5003 hc->id = HFC_cnt;
5004 hc->pcm = pcm[HFC_cnt];
5005 hc->io_mode = iomode[HFC_cnt];
5006 if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5013 hc->dnum[pt] = ch;
5014 hc->bmask[pt] = bmask[bmask_cnt++];
5015 if ((maskcheck & hc->bmask[pt])
5016 || (dmask[E1_cnt] & hc->bmask[pt])) {
5018 "HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5021 return -EINVAL;
5023 maskcheck |= hc->bmask[pt];
5025 "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5026 E1_cnt + 1, ch, hc->bmask[pt]);
5029 hc->ports = pt;
5031 if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5033 hc->dnum[0] = 16;
5034 hc->bmask[0] = 0xfffefffe;
5035 hc->ports = 1;
5039 hc->masterclk = -1;
5041 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5042 hc->silence = 0xff; /* ulaw silence */
5044 hc->silence = 0x2a; /* alaw silence */
5045 if ((poll >> 1) > sizeof(hc->silence_data)) {
5049 return -EINVAL;
5052 hc->silence_data[i] = hc->silence;
5054 if (hc->ctype != HFC_TYPE_XHFC) {
5056 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5057 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5061 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5063 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5064 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5067 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5069 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5070 hc->slots = 32;
5072 hc->slots = 64;
5074 hc->slots = 128;
5076 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5077 hc->wdcount = 0;
5078 hc->wdbyte = V_GPIO_OUT2;
5083 /* setup pci, hc->slots may change due to PLXSD */
5091 ret_err = -EIO;
5101 hc->HFC_outb_nodebug = hc->HFC_outb;
5102 hc->HFC_inb_nodebug = hc->HFC_inb;
5103 hc->HFC_inw_nodebug = hc->HFC_inw;
5104 hc->HFC_wait_nodebug = hc->HFC_wait;
5106 hc->HFC_outb = HFC_outb_debug;
5107 hc->HFC_inb = HFC_inb_debug;
5108 hc->HFC_inw = HFC_inw_debug;
5109 hc->HFC_wait = HFC_wait_debug;
5112 for (pt = 0; pt < hc->ports; pt++) {
5114 printk(KERN_ERR "too many ports (max=%d).\n",
5116 ret_err = -EINVAL;
5119 if (hc->ctype == HFC_TYPE_E1)
5125 "%s: Registering D-channel, card(%d) port(%d) "
5130 while (pt) { /* release already registered ports */
5131 pt--;
5132 if (hc->ctype == HFC_TYPE_E1)
5134 hc->chan[hc->dnum[pt]].dch);
5137 hc->chan[(pt << 2) + 2].dch);
5141 if (hc->ctype != HFC_TYPE_E1)
5144 if (hc->ctype == HFC_TYPE_E1) {
5150 switch (m->dip_type) {
5164 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5168 m->vendor_name, m->card_name, dips, pmj);
5177 outw(0x4000, hc->pci_iobase + 4);
5182 dips = inb(hc->pci_iobase);
5183 dips = inb(hc->pci_iobase);
5184 dips = inb(hc->pci_iobase);
5185 dips = ~inb(hc->pci_iobase) & 0x3F;
5186 outw(0x0, hc->pci_iobase + 4);
5190 m->vendor_name, m->card_name, dips);
5199 m->vendor_name, m->card_name, dips);
5205 list_add_tail(&hc->list, &HFClist);
5210 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5213 hc->irq = (m->irq) ? : hc->pci_dev->irq;
5222 spin_lock_irqsave(&hc->lock, flags);
5224 spin_unlock_irqrestore(&hc->lock, flags);
5243 pdev->vendor, pdev->device,
5244 pdev->subsystem_vendor, pdev->subsystem_device);
5264 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5265 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5266 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5267 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5268 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5269 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5270 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5271 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5272 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5273 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5274 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5275 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5277 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5278 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5280 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5281 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5283 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5284 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5285 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5287 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5288 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5289 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5290 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5292 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5293 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5294 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5296 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5298 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5300 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5301 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5302 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5303 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5305 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5306 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5307 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5314 /* Cards with HFC-4S Chip */
5348 /* Cards with HFC-8S Chip */
5369 /* Cards with HFC-E1 Chip */
5406 struct hm_map *m = (struct hm_map *)ent->driver_data;
5409 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5410 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5411 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5412 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5415 "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5416 pdev->device, pdev->subsystem_vendor,
5417 pdev->subsystem_device);
5420 return -ENODEV;
5455 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5490 err = -EINVAL;