17 #include "iommu.h"
114 	struct intel_iommu *iommu;  in iommu_regset_show()  local
120 	for_each_active_iommu(iommu, drhd) {  in iommu_regset_show()
122 			seq_puts(m, "IOMMU: Invalid base address\n");  in iommu_regset_show()
127 		seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",  in iommu_regset_show()
128 			   iommu->name, drhd->reg_base_addr);  in iommu_regset_show()
134 		raw_spin_lock_irqsave(&iommu->register_lock, flag);  in iommu_regset_show()
136 			value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);  in iommu_regset_show()
142 			value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);  in iommu_regset_show()
147 		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in iommu_regset_show()
215 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)  in ctx_tbl_walk()  argument
237 		context = iommu_context_addr(iommu, bus, devfn, 0);  in ctx_tbl_walk()
246 		tbl_wlk.rt_entry = &iommu->root_entry[bus];  in ctx_tbl_walk()
250 		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {  in ctx_tbl_walk()
261 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)  in root_tbl_walk()  argument
265 	spin_lock(&iommu->lock);  in root_tbl_walk()
266 	seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,  in root_tbl_walk()
267 		   (u64)virt_to_phys(iommu->root_entry));  in root_tbl_walk()
276 		ctx_tbl_walk(m, iommu, bus);  in root_tbl_walk()
277 	spin_unlock(&iommu->lock);  in root_tbl_walk()
283 	struct intel_iommu *iommu;  in dmar_translation_struct_show()  local
287 	for_each_active_iommu(iommu, drhd) {  in dmar_translation_struct_show()
288 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in dmar_translation_struct_show()
291 				   iommu->name);  in dmar_translation_struct_show()
294 		root_tbl_walk(m, iommu);  in dmar_translation_struct_show()
351 	struct intel_iommu *iommu;  in domain_translation_struct_show()  local
359 	for_each_active_iommu(iommu, drhd) {  in domain_translation_struct_show()
364 		if (seg != iommu->segment)  in domain_translation_struct_show()
367 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in domain_translation_struct_show()
370 				   iommu->name);  in domain_translation_struct_show()
373 		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)  in domain_translation_struct_show()
379 		 * The iommu->lock is held across the callback, which will  in domain_translation_struct_show()
387 		spin_lock(&iommu->lock);  in domain_translation_struct_show()
389 		context = iommu_context_addr(iommu, bus, devfn, 0);  in domain_translation_struct_show()
454 			   iommu->segment, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));  in domain_translation_struct_show()
467 		spin_unlock(&iommu->lock);  in domain_translation_struct_show()
494 					  struct intel_iommu *iommu)  in invalidation_queue_entry_show()  argument
496 	int index, shift = qi_shift(iommu);  in invalidation_queue_entry_show()
500 	if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
507 		desc = iommu->qi->desc + offset;  in invalidation_queue_entry_show()
508 		if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
512 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
516 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
523 	struct intel_iommu *iommu;  in invalidation_queue_show()  local
529 	for_each_active_iommu(iommu, drhd) {  in invalidation_queue_show()
530 		qi = iommu->qi;  in invalidation_queue_show()
531 		shift = qi_shift(iommu);  in invalidation_queue_show()
533 		if (!qi || !ecap_qis(iommu->ecap))  in invalidation_queue_show()
536 		seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);  in invalidation_queue_show()
541 			   dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,  in invalidation_queue_show()
542 			   dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);  in invalidation_queue_show()
543 		invalidation_queue_entry_show(m, iommu);  in invalidation_queue_show()
555 				    struct intel_iommu *iommu)  in ir_tbl_remap_entry_show()  argument
565 		ri_entry = &iommu->ir_table->base[idx];  in ir_tbl_remap_entry_show()
579 				     struct intel_iommu *iommu)  in ir_tbl_posted_entry_show()  argument
589 		pi_entry = &iommu->ir_table->base[idx];  in ir_tbl_posted_entry_show()
611 	struct intel_iommu *iommu;  in ir_translation_struct_show()  local
616 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
617 		if (!ecap_ir_support(iommu->ecap))  in ir_translation_struct_show()
620 		seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",  in ir_translation_struct_show()
621 			   iommu->name);  in ir_translation_struct_show()
623 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in ir_translation_struct_show()
624 		if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {  in ir_translation_struct_show()
625 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
627 			ir_tbl_remap_entry_show(m, iommu);  in ir_translation_struct_show()
636 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
637 		if (!cap_pi_support(iommu->cap))  in ir_translation_struct_show()
640 		seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",  in ir_translation_struct_show()
641 			   iommu->name);  in ir_translation_struct_show()
643 		if (iommu->ir_table) {  in ir_translation_struct_show()
644 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
646 			ir_tbl_posted_entry_show(m, iommu);  in ir_translation_struct_show()
659 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,  in latency_show_one()  argument
662 	seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",  in latency_show_one()
663 		   iommu->name, drhd->reg_base_addr);  in latency_show_one()
665 	dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);  in latency_show_one()
672 	struct intel_iommu *iommu;  in latency_show()  local
675 	for_each_active_iommu(iommu, drhd)  in latency_show()
676 		latency_show_one(m, iommu, drhd);  in latency_show()
692 	struct intel_iommu *iommu;  in dmar_perf_latency_write()  local
710 		for_each_active_iommu(iommu, drhd) {  in dmar_perf_latency_write()
711 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
712 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
713 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
719 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
720 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
725 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
726 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
731 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
732 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
773  * /sys/kernel/debug/iommu/intel/0000:00:01.0/domain_translation_struct
793  * /sys/kernel/debug/iommu/intel/0000:00:01.0/1/domain_translation_struct