hw/mlx5/cq.c

85 	struct mlx5_cqe64 *cqe64;
87 	cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
89 	if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) &&
90 	    !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
344 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
456 	struct mlx5_cqe64 *cqe64;
470 	cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
479 	opcode = get_cqe_opcode(cqe64);
492 	qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
506 		wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
508 		handle_good_req(wc, cqe64, wq, idx);
509 		handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
518 		handle_responder(wc, cqe64, *cur_qp);
525 		err_cqe = (struct mlx5_err_cqe *)cqe64;
538 			wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
547 				wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
559 			(struct mlx5_sig_err_cqe *)cqe64;
878 	struct mlx5_cqe64 *cqe64;
882 		cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
883 		cqe64->op_own = MLX5_CQE_INVALID << 4;
1086 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1088 	return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1093 	struct mlx5_cqe64 *cqe64, *dest64;
1117 		cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1118 		if (is_equal_rsn(cqe64, rsn)) {
1119 			if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1120 				mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));