Lines Matching defs:bits

274 	/* Clear those bits which are not active anymore */
459 	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
520 		 * The order of the bits in the AXI-XADC status register does
521 		 * not match the order of the bits in the XADC alarm enable
542 	 * The order of the bits in the AXI-XADC status register does not match
543 	 * the order of the bits in the XADC alarm enable register. We get
572 	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
775 	 * As per datasheet the power-down bits are don't care in the
865 	 * the same time. In this mode the upper 8 bits in the sequencer
866 	 * register are don't care and the lower 8 bits control two channels
918 	unsigned int bits = chan->scan_type.realbits;
934 			*val = sign_extend32(val16, bits - 1);
940 			/* V = (val * 3.0) / 2**bits */
956 			*val2 = bits;
960 			*val2 = bits;
967 		*val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);