iio/adc/rzg2l_adc.c

14 #include <linux/iio/adc-helpers.h>
26 #define DRIVER_NAME		"rzg2l-adc"
117 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
119 	return readl(adc->base + reg);
122 static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
124 	writel(val, adc->base + reg);
127 static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
131 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
136 	rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
140 static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
145 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
150 	rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
156 				200, 1000, true, adc, RZG2L_ADM(0));
161 static void rzg2l_set_trigger(struct rzg2l_adc *adc)
172 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
177 	rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
188 static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
190 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
194 	if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
197 	rzg2l_set_trigger(adc);
200 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
203 	rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
205 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
208 	rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
216 	reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
220 	rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
225 static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
227 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
235 	ret = rzg2l_adc_conversion_setup(adc, ch);
239 	reinit_completion(&adc->completion);
241 	rzg2l_adc_start_stop(adc, true);
243 	if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
244 		rzg2l_adc_writel(adc, RZG2L_ADINT,
245 				 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);
249 	rzg2l_adc_start_stop(adc, false);
261 	struct rzg2l_adc *adc = iio_priv(indio_dev);
269 		guard(mutex)(&adc->lock);
271 		ret = rzg2l_adc_conversion(indio_dev, adc, chan->channel);
275 		*val = adc->last_val[chan->channel];
299 	struct rzg2l_adc *adc = dev_id;
300 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
305 	reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
309 		rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
318 		adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
321 	rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
323 	complete(&adc->completion);
333 static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
335 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
365 	adc->data = data;
370 static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc)
372 	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
381 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
383 	rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
386 				200, 1000, false, adc, RZG2L_ADM(0));
392 		reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
395 		rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
404 	reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
411 	rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
423 	struct rzg2l_adc *adc;
427 	indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
431 	adc = iio_priv(indio_dev);
433 	adc->hw_params = device_get_match_data(dev);
434 	if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS)
437 	ret = rzg2l_adc_parse_properties(pdev, adc);
441 	mutex_init(&adc->lock);
443 	adc->base = devm_platform_ioremap_resource(pdev, 0);
444 	if (IS_ERR(adc->base))
445 		return PTR_ERR(adc->base);
447 	adc->adrstn = devm_reset_control_get_exclusive_deasserted(dev, "adrst-n");
448 	if (IS_ERR(adc->adrstn))
449 		return dev_err_probe(dev, PTR_ERR(adc->adrstn),
452 	adc->presetn = devm_reset_control_get_exclusive_deasserted(dev, "presetn");
453 	if (IS_ERR(adc->presetn))
454 		return dev_err_probe(dev, PTR_ERR(adc->presetn),
465 	ret = rzg2l_adc_hw_init(dev, adc);
475 			       0, dev_name(dev), adc);
479 	init_completion(&adc->completion);
484 	indio_dev->channels = adc->data->channels;
485 	indio_dev->num_channels = adc->data->num_channels;
508 	{ .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
509 	{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
517 	struct rzg2l_adc *adc = iio_priv(indio_dev);
519 	rzg2l_adc_pwr(adc, false);
527 	struct rzg2l_adc *adc = iio_priv(indio_dev);
529 	rzg2l_adc_pwr(adc, true);
537 	struct rzg2l_adc *adc = iio_priv(indio_dev);
539 		{ .rstc = adc->presetn },
540 		{ .rstc = adc->adrstn },
545 		adc->was_rpm_active = false;
550 		adc->was_rpm_active = true;
560 	if (adc->was_rpm_active)
569 	struct rzg2l_adc *adc = iio_priv(indio_dev);
571 		{ .rstc = adc->adrstn },
572 		{ .rstc = adc->presetn },
580 	if (adc->was_rpm_active) {
586 	ret = rzg2l_adc_hw_init(dev, adc);
593 	if (adc->was_rpm_active) {