iio/adc/imx8qxp-adc.c

30 #define ADC_DRIVER_NAME		"imx8qxp-adc"
123 static void imx8qxp_adc_reset(struct imx8qxp_adc *adc)
128 	ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
130 	writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
133 	writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
137 	writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
140 static void imx8qxp_adc_reg_config(struct imx8qxp_adc *adc, int channel)
150 	writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG);
157 	writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0));
165 	writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0));
173 	writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0));
176 static void imx8qxp_adc_fifo_config(struct imx8qxp_adc *adc)
180 	fifo_ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL);
184 	writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL);
187 	interrupt_en = readl(adc->regs + IMX8QXP_ADR_ADC_IE);
189 	writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE);
192 static void imx8qxp_adc_disable(struct imx8qxp_adc *adc)
196 	ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
198 	writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
205 	struct imx8qxp_adc *adc = iio_priv(indio_dev);
206 	struct device *dev = adc->dev;
215 		mutex_lock(&adc->lock);
216 		reinit_completion(&adc->completion);
218 		imx8qxp_adc_reg_config(adc, chan->channel);
220 		imx8qxp_adc_fifo_config(adc);
222 		/* adc enable */
223 		ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
225 		writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
226 		/* adc start */
227 		writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG);
229 		ret = wait_for_completion_interruptible_timeout(&adc->completion,
236 			mutex_unlock(&adc->lock);
240 			mutex_unlock(&adc->lock);
244 		*val = adc->fifo[0];
246 		mutex_unlock(&adc->lock);
250 		ret = regulator_get_voltage(adc->vref);
258 		*val = clk_get_rate(adc->clk) / 3;
268 	struct imx8qxp_adc *adc = dev_id;
273 			       readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
276 		adc->fifo[i] = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
277 				readl_relaxed(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
280 		complete(&adc->completion);
288 	struct imx8qxp_adc *adc = iio_priv(indio_dev);
289 	struct device *dev = adc->dev;
296 	*readval = readl(adc->regs + reg);
311 	struct imx8qxp_adc *adc;
317 	indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
323 	adc = iio_priv(indio_dev);
324 	adc->dev = dev;
326 	mutex_init(&adc->lock);
327 	adc->regs = devm_platform_ioremap_resource(pdev, 0);
328 	if (IS_ERR(adc->regs))
329 		return PTR_ERR(adc->regs);
335 	adc->clk = devm_clk_get(dev, "per");
336 	if (IS_ERR(adc->clk))
337 		return dev_err_probe(dev, PTR_ERR(adc->clk), "Failed getting clock\n");
339 	adc->ipg_clk = devm_clk_get(dev, "ipg");
340 	if (IS_ERR(adc->ipg_clk))
341 		return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), "Failed getting clock\n");
343 	adc->vref = devm_regulator_get(dev, "vref");
344 	if (IS_ERR(adc->vref))
345 		return dev_err_probe(dev, PTR_ERR(adc->vref), "Failed getting reference voltage\n");
347 	ret = regulator_enable(adc->vref);
349 		dev_err(dev, "Can't enable adc reference top voltage\n");
355 	init_completion(&adc->completion);
363 	ret = clk_prepare_enable(adc->clk);
369 	ret = clk_prepare_enable(adc->ipg_clk);
375 	ret = devm_request_irq(dev, irq, imx8qxp_adc_isr, 0, ADC_DRIVER_NAME, adc);
381 	imx8qxp_adc_reset(adc);
385 		imx8qxp_adc_disable(adc);
398 	clk_disable_unprepare(adc->ipg_clk);
400 	clk_disable_unprepare(adc->clk);
402 	regulator_disable(adc->vref);
410 	struct imx8qxp_adc *adc = iio_priv(indio_dev);
411 	struct device *dev = adc->dev;
417 	imx8qxp_adc_disable(adc);
419 	clk_disable_unprepare(adc->clk);
420 	clk_disable_unprepare(adc->ipg_clk);
421 	regulator_disable(adc->vref);
430 	struct imx8qxp_adc *adc = iio_priv(indio_dev);
432 	imx8qxp_adc_disable(adc);
434 	clk_disable_unprepare(adc->clk);
435 	clk_disable_unprepare(adc->ipg_clk);
436 	regulator_disable(adc->vref);
444 	struct imx8qxp_adc *adc = iio_priv(indio_dev);
447 	ret = regulator_enable(adc->vref);
449 		dev_err(dev, "Can't enable adc reference top voltage, err = %d\n", ret);
453 	ret = clk_prepare_enable(adc->clk);
459 	ret = clk_prepare_enable(adc->ipg_clk);
465 	imx8qxp_adc_reset(adc);
470 	clk_disable_unprepare(adc->clk);
473 	regulator_disable(adc->vref);
483 	{ .compatible = "nxp,imx8qxp-adc", },