Lines Matching full:info
163 void (*init_hw)(struct exynos_adc *info);
164 void (*exit_hw)(struct exynos_adc *info);
165 void (*clear_irq)(struct exynos_adc *info);
166 void (*start_conv)(struct exynos_adc *info, unsigned long addr);
169 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
171 if (info->data->needs_sclk)
172 clk_unprepare(info->sclk);
173 clk_unprepare(info->clk);
176 static int exynos_adc_prepare_clk(struct exynos_adc *info)
180 ret = clk_prepare(info->clk);
182 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
186 if (info->data->needs_sclk) {
187 ret = clk_prepare(info->sclk);
189 clk_unprepare(info->clk);
190 dev_err(info->dev,
199 static void exynos_adc_disable_clk(struct exynos_adc *info)
201 if (info->data->needs_sclk)
202 clk_disable(info->sclk);
203 clk_disable(info->clk);
206 static int exynos_adc_enable_clk(struct exynos_adc *info)
210 ret = clk_enable(info->clk);
212 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
216 if (info->data->needs_sclk) {
217 ret = clk_enable(info->sclk);
219 clk_disable(info->clk);
220 dev_err(info->dev,
229 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
233 if (info->data->needs_adc_phy)
234 regmap_write(info->pmu_map, info->data->phy_offset, 1);
241 writel(con1, ADC_V1_CON(info->regs));
244 writel(info->delay, ADC_V1_DLY(info->regs));
247 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
251 if (info->data->needs_adc_phy)
252 regmap_write(info->pmu_map, info->data->phy_offset, 0);
254 con = readl(ADC_V1_CON(info->regs));
256 writel(con, ADC_V1_CON(info->regs));
259 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
261 writel(1, ADC_V1_INTCLR(info->regs));
264 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
269 writel(addr, ADC_V1_MUX(info->regs));
271 con1 = readl(ADC_V1_CON(info->regs));
272 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
310 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
316 con1 = readl(ADC_V1_CON(info->regs));
318 writel(con1, ADC_V1_CON(info->regs));
321 writel(addr, ADC_S3C2410_MUX(info->regs));
323 con1 = readl(ADC_V1_CON(info->regs));
324 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
336 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
342 writel(addr, ADC_S3C2410_MUX(info->regs));
344 con1 = readl(ADC_V1_CON(info->regs));
345 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
357 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
362 con1 = readl(ADC_V1_CON(info->regs));
365 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
387 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
391 if (info->data->needs_adc_phy)
392 regmap_write(info->pmu_map, info->data->phy_offset, 1);
395 writel(con1, ADC_V2_CON1(info->regs));
399 writel(con2, ADC_V2_CON2(info->regs));
402 writel(1, ADC_V2_INT_EN(info->regs));
405 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
409 if (info->data->needs_adc_phy)
410 regmap_write(info->pmu_map, info->data->phy_offset, 0);
412 con = readl(ADC_V2_CON1(info->regs));
414 writel(con, ADC_V2_CON1(info->regs));
417 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
419 writel(1, ADC_V2_INT_ST(info->regs));
422 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
427 con2 = readl(ADC_V2_CON2(info->regs));
430 writel(con2, ADC_V2_CON2(info->regs));
432 con1 = readl(ADC_V2_CON1(info->regs));
433 writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
461 static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
466 writel(con1, ADC_V2_CON1(info->regs));
468 con2 = readl(ADC_V2_CON2(info->regs));
471 writel(con2, ADC_V2_CON2(info->regs));
474 writel(1, ADC_V2_INT_EN(info->regs));
540 struct exynos_adc *info = iio_priv(indio_dev);
545 ret = regulator_get_voltage(info->vdd);
551 *val2 = info->data->mask;
558 mutex_lock(&info->lock);
559 reinit_completion(&info->completion);
562 if (info->data->start_conv)
563 info->data->start_conv(info, chan->address);
565 time_left = wait_for_completion_timeout(&info->completion,
569 if (info->data->init_hw)
570 info->data->init_hw(info);
573 *val = info->value;
578 mutex_unlock(&info->lock);
585 struct exynos_adc *info = iio_priv(indio_dev);
589 mutex_lock(&info->lock);
590 info->read_ts = true;
592 reinit_completion(&info->completion);
595 ADC_V1_TSC(info->regs));
598 info->data->start_conv(info, ADC_S3C2410_MUX_TS);
600 time_left = wait_for_completion_timeout(&info->completion,
604 if (info->data->init_hw)
605 info->data->init_hw(info);
608 *x = info->ts_x;
609 *y = info->ts_y;
613 info->read_ts = false;
614 mutex_unlock(&info->lock);
621 struct exynos_adc *info = dev_id;
622 u32 mask = info->data->mask;
625 if (info->read_ts) {
626 info->ts_x = readl(ADC_V1_DATX(info->regs));
627 info->ts_y = readl(ADC_V1_DATY(info->regs));
628 writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs));
630 info->value = readl(ADC_V1_DATX(info->regs)) & mask;
634 if (info->data->clear_irq)
635 info->data->clear_irq(info);
637 complete(&info->completion);
651 struct exynos_adc *info = dev_id;
652 struct iio_dev *dev = dev_get_drvdata(info->dev);
657 while (READ_ONCE(info->ts_enabled)) {
664 input_report_key(info->input, BTN_TOUCH, 0);
665 input_sync(info->input);
669 input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK);
670 input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK);
671 input_report_key(info->input, BTN_TOUCH, 1);
672 input_sync(info->input);
677 writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
686 struct exynos_adc *info = iio_priv(indio_dev);
691 *readval = readl(info->regs + reg);
735 struct exynos_adc *info = input_get_drvdata(dev);
737 WRITE_ONCE(info->ts_enabled, true);
738 enable_irq(info->tsirq);
745 struct exynos_adc *info = input_get_drvdata(dev);
747 WRITE_ONCE(info->ts_enabled, false);
748 disable_irq(info->tsirq);
751 static int exynos_adc_ts_init(struct exynos_adc *info)
755 if (info->tsirq <= 0)
758 info->input = input_allocate_device();
759 if (!info->input)
762 info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
763 info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
765 input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0);
766 input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0);
768 info->input->name = "S3C24xx TouchScreen";
769 info->input->id.bustype = BUS_HOST;
770 info->input->open = exynos_adc_ts_open;
771 info->input->close = exynos_adc_ts_close;
773 input_set_drvdata(info->input, info);
775 ret = input_register_device(info->input);
777 input_free_device(info->input);
781 ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr,
783 "touchscreen", info);
785 input_unregister_device(info->input);
792 struct exynos_adc *info = NULL;
806 info = iio_priv(indio_dev);
808 info->data = exynos_adc_get_data(pdev);
809 if (!info->data) {
814 info->regs = devm_platform_ioremap_resource(pdev, 0);
815 if (IS_ERR(info->regs))
816 return PTR_ERR(info->regs);
819 if (info->data->needs_adc_phy) {
820 info->pmu_map = syscon_regmap_lookup_by_phandle(
823 if (IS_ERR(info->pmu_map)) {
825 return PTR_ERR(info->pmu_map);
838 info->irq = irq;
845 info->tsirq = irq;
847 info->tsirq = -1;
850 info->dev = &pdev->dev;
852 init_completion(&info->completion);
854 info->clk = devm_clk_get(&pdev->dev, "adc");
855 if (IS_ERR(info->clk)) {
857 PTR_ERR(info->clk));
858 return PTR_ERR(info->clk);
861 if (info->data->needs_sclk) {
862 info->sclk = devm_clk_get(&pdev->dev, "sclk");
863 if (IS_ERR(info->sclk)) {
866 PTR_ERR(info->sclk));
867 return PTR_ERR(info->sclk);
871 info->vdd = devm_regulator_get(&pdev->dev, "vdd");
872 if (IS_ERR(info->vdd))
873 return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd),
876 ret = regulator_enable(info->vdd);
880 ret = exynos_adc_prepare_clk(info);
884 ret = exynos_adc_enable_clk(info);
891 indio_dev->info = &exynos_adc_iio_info;
894 indio_dev->num_channels = info->data->num_channels;
896 mutex_init(&info->lock);
898 ret = request_irq(info->irq, exynos_adc_isr,
899 0, dev_name(&pdev->dev), info);
902 info->irq);
910 if (info->data->init_hw)
911 info->data->init_hw(info);
914 info->delay = pdata->delay;
916 info->delay = 10000;
919 ret = exynos_adc_ts_init(info);
935 input_unregister_device(info->input);
936 free_irq(info->tsirq, info);
941 free_irq(info->irq, info);
943 if (info->data->exit_hw)
944 info->data->exit_hw(info);
945 exynos_adc_disable_clk(info);
947 exynos_adc_unprepare_clk(info);
949 regulator_disable(info->vdd);
956 struct exynos_adc *info = iio_priv(indio_dev);
958 if (IS_REACHABLE(CONFIG_INPUT) && info->input) {
959 free_irq(info->tsirq, info);
960 input_unregister_device(info->input);
965 free_irq(info->irq, info);
966 if (info->data->exit_hw)
967 info->data->exit_hw(info);
968 exynos_adc_disable_clk(info);
969 exynos_adc_unprepare_clk(info);
970 regulator_disable(info->vdd);
976 struct exynos_adc *info = iio_priv(indio_dev);
978 if (info->data->exit_hw)
979 info->data->exit_hw(info);
980 exynos_adc_disable_clk(info);
981 regulator_disable(info->vdd);
989 struct exynos_adc *info = iio_priv(indio_dev);
992 ret = regulator_enable(info->vdd);
996 ret = exynos_adc_enable_clk(info);
1000 if (info->data->init_hw)
1001 info->data->init_hw(info);