Lines Matching defs:rate
22 #define WAIT_PCLK(n, rate) \
23 ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10)
66 #define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
69 #define SYNQUACER_I2C_CLK_MASTER_STD(rate) \
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
72 #define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
77 #define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
82 #define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00
85 #define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
90 #define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00
94 #define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \
95 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
99 #define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \
100 (((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \
104 #define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \
105 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
109 #define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \
110 (((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \
550 device_property_read_u32(&pdev->dev, "socionext,pclk-rate",