Lines Matching refs:bus
30 * of the bus.
596 bool ber_state; /* Indicate the bus error state */
599 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
602 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
608 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
611 static void npcm_i2c_init_params(struct npcm_i2c *bus)
613 bus->stop_ind = I2C_NO_STATUS_IND;
614 bus->rd_size = 0;
615 bus->wr_size = 0;
616 bus->rd_ind = 0;
617 bus->wr_ind = 0;
618 bus->read_block_use = false;
619 bus->int_time_stamp = 0;
620 bus->PEC_use = false;
621 bus->PEC_mask = 0;
623 if (bus->slave)
624 bus->master_or_slave = I2C_SLAVE;
628 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
630 iowrite8(data, bus->reg + NPCM_I2CSDA);
633 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
635 return ioread8(bus->reg + NPCM_I2CSDA);
640 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
642 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
647 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
649 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
652 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
654 if (bus->operation == I2C_READ_OPER)
655 return bus->rd_ind;
656 if (bus->operation == I2C_WRITE_OPER)
657 return bus->wr_ind;
662 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
664 return bus->wr_size == 0 && bus->rd_size == 0;
667 static void npcm_i2c_disable(struct npcm_i2c *bus)
676 iowrite8(0, bus->reg + npcm_i2caddr[i]);
680 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
682 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
684 bus->state = I2C_DISABLE;
687 static void npcm_i2c_enable(struct npcm_i2c *bus)
689 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
692 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
693 bus->state = I2C_IDLE;
697 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
702 val = ioread8(bus->reg + NPCM_I2CCST3);
704 iowrite8(val, bus->reg + NPCM_I2CCST3);
706 val = ioread8(bus->reg + NPCM_I2CCTL1);
712 iowrite8(val, bus->reg + NPCM_I2CCTL1);
715 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
719 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
721 if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
728 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
732 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
734 if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
741 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
745 val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
747 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
750 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
754 val = ioread8(bus->reg + NPCM_I2CTXF_STS);
756 iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
759 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
763 val = ioread8(bus->reg + NPCM_I2CRXF_STS);
765 iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
768 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
772 val = ioread8(bus->reg + NPCM_I2CCTL1);
778 iowrite8(val, bus->reg + NPCM_I2CCTL1);
781 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
785 val = ioread8(bus->reg + NPCM_I2CCTL1);
788 iowrite8(val, bus->reg + NPCM_I2CCTL1);
791 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
801 val = ioread8(bus->reg + NPCM_I2CCTL1);
804 iowrite8(val, bus->reg + NPCM_I2CCTL1);
806 if (!bus->fifo_use)
809 npcm_i2c_select_bank(bus, I2C_BANK_1);
811 if (bus->operation == I2C_READ_OPER)
812 npcm_i2c_clear_rx_fifo(bus);
814 npcm_i2c_clear_tx_fifo(bus);
815 npcm_i2c_clear_fifo_int(bus);
816 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
819 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
823 val = ioread8(bus->reg + NPCM_I2CCTL1);
829 iowrite8(val, bus->reg + NPCM_I2CCTL1);
832 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
836 val = ioread8(bus->reg + NPCM_I2CCTL1);
839 iowrite8(val, bus->reg + NPCM_I2CCTL1);
842 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
848 iowrite8(val, bus->reg + NPCM_I2CST);
852 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
857 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
863 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
866 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
875 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
880 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
883 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
888 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
892 dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
898 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
899 npcm_i2c_slave_int_enable(bus, enable);
905 static void npcm_i2c_reset(struct npcm_i2c *bus)
916 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
918 npcm_i2c_disable(bus);
919 npcm_i2c_enable(bus);
923 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
926 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
927 iowrite8(0xFF, bus->reg + NPCM_I2CST);
930 npcm_i2c_eob_int(bus, false);
933 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
936 if (bus->slave) {
937 addr = bus->slave->addr;
938 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
943 npcm_i2c_clear_master_status(bus);
945 bus->state = I2C_IDLE;
948 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
950 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
953 static void npcm_i2c_callback(struct npcm_i2c *bus,
960 msgs = bus->msgs;
961 msgs_num = bus->msgs_num;
969 if (completion_done(&bus->cmd_complete))
974 bus->cmd_err = bus->msgs_num;
975 if (bus->tx_complete_cnt < ULLONG_MAX)
976 bus->tx_complete_cnt++;
980 if (bus->msgs) {
991 bus->cmd_err = -ENXIO;
996 bus->cmd_err = -EAGAIN;
1006 bus->operation = I2C_NO_OPER;
1008 if (bus->slave)
1009 bus->master_or_slave = I2C_SLAVE;
1012 complete(&bus->cmd_complete);
1015 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
1017 if (bus->operation == I2C_WRITE_OPER)
1018 return (bus->data->txf_sts_tx_bytes &
1019 ioread8(bus->reg + NPCM_I2CTXF_STS));
1020 if (bus->operation == I2C_READ_OPER)
1021 return (bus->data->rxf_sts_rx_bytes &
1022 ioread8(bus->reg + NPCM_I2CRXF_STS));
1026 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
1034 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
1036 if (bus->wr_ind < bus->wr_size)
1037 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1039 npcm_i2c_wr_byte(bus, 0xFF);
1040 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
1049 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
1053 if (!bus->fifo_use)
1055 npcm_i2c_select_bank(bus, I2C_BANK_1);
1056 npcm_i2c_clear_tx_fifo(bus);
1057 npcm_i2c_clear_rx_fifo(bus);
1061 rxf_ctl = min_t(int, nread, bus->data->fifo_size);
1064 if (nread <= bus->data->fifo_size)
1065 rxf_ctl |= bus->data->rxf_ctl_last_pec;
1072 if (bus->rd_ind == 0 && bus->read_block_use) {
1078 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
1083 if (nwrite > bus->data->fifo_size)
1085 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
1087 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
1089 npcm_i2c_clear_tx_fifo(bus);
1093 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
1098 data = npcm_i2c_rd_byte(bus);
1099 if (bus->rd_ind < bus->rd_size)
1100 bus->rd_buf[bus->rd_ind++] = data;
1104 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
1107 if (!npcm_i2c_is_master(bus))
1110 npcm_i2c_eob_int(bus, true);
1111 npcm_i2c_master_stop(bus);
1112 npcm_i2c_clear_master_status(bus);
1116 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
1119 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
1121 return ioread8(bus->reg + npcm_i2caddr[addr_type]);
1124 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
1132 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
1133 iowrite8(0, bus->reg + npcm_i2caddr[i]);
1139 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
1145 npcm_i2c_clear_fifo_int(bus);
1146 npcm_i2c_clear_tx_fifo(bus);
1147 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1148 while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
1149 if (bus->slv_wr_size <= 0)
1151 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
1152 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
1153 bus->slv_wr_ind++;
1154 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
1155 bus->slv_wr_size--;
1159 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
1163 if (!bus->slave)
1167 data = npcm_i2c_rd_byte(bus);
1169 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
1170 bus->slv_rd_buf[bus->slv_rd_ind] = data;
1171 bus->slv_rd_ind++;
1174 if (bus->slv_rd_ind == 1 && bus->read_block_use)
1175 bus->slv_rd_size = data + bus->PEC_use + 1;
1179 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
1184 int ret = bus->slv_wr_ind;
1187 for (i = 0; i < bus->data->fifo_size; i++) {
1188 if (bus->slv_wr_size >= bus->data->fifo_size)
1190 if (bus->state == I2C_SLAVE_MATCH) {
1191 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
1192 bus->state = I2C_OPER_STARTED;
1194 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
1196 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
1197 bus->slv_wr_buf[ind] = value;
1198 bus->slv_wr_size++;
1200 return bus->data->fifo_size - ret;
1203 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
1207 for (i = 0; i < bus->slv_rd_ind; i++)
1208 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
1209 &bus->slv_rd_buf[i]);
1214 if (bus->slv_rd_ind) {
1215 bus->slv_wr_size = 0;
1216 bus->slv_wr_ind = 0;
1219 bus->slv_rd_ind = 0;
1220 bus->slv_rd_size = bus->adap.quirks->max_read_len;
1222 npcm_i2c_clear_fifo_int(bus);
1223 npcm_i2c_clear_rx_fifo(bus);
1226 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
1229 bus->state = I2C_OPER_STARTED;
1230 bus->operation = I2C_READ_OPER;
1231 bus->slv_rd_size = nread;
1232 bus->slv_rd_ind = 0;
1234 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1235 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1236 npcm_i2c_clear_tx_fifo(bus);
1237 npcm_i2c_clear_rx_fifo(bus);
1240 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
1246 bus->operation = I2C_WRITE_OPER;
1249 npcm_i2c_slave_get_wr_buf(bus);
1250 npcm_i2c_write_fifo_slave(bus, nwrite);
1258 * to the FIFO and onward to the bus.
1259 * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1264 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1268 left_in_fifo = bus->data->txf_sts_tx_bytes &
1269 ioread8(bus->reg + NPCM_I2CTXF_STS);
1272 if (left_in_fifo >= bus->data->fifo_size ||
1273 bus->slv_wr_size >= bus->data->fifo_size)
1277 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1278 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1280 if (bus->slv_wr_ind < 0)
1281 bus->slv_wr_ind += bus->data->fifo_size;
1284 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1286 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1291 bus->operation = I2C_WRITE_OPER;
1292 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1293 bus->slv_wr_buf);
1301 bus->operation = I2C_READ_OPER;
1302 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1303 bus->stop_ind = I2C_SLAVE_RCV_IND;
1304 npcm_i2c_slave_send_rd_buf(bus);
1305 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1306 bus->slv_rd_buf);
1310 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1314 u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1318 bus->stop_ind = I2C_NACK_IND;
1319 npcm_i2c_slave_wr_buf_sync(bus);
1320 if (bus->fifo_use)
1323 bus->reg + NPCM_I2CFIF_CTS);
1326 bus->stop_ind = I2C_NO_STATUS_IND;
1327 bus->operation = I2C_NO_OPER;
1328 bus->own_slave_addr = 0xFF;
1334 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1342 * Check whether bus arbitration or Start or Stop during data
1343 * xfer bus arbitration problem should not result in recovery
1345 bus->stop_ind = I2C_BUS_ERR_IND;
1347 /* wait for bus busy before clear fifo */
1348 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1350 bus->state = I2C_IDLE;
1356 if (completion_done(&bus->cmd_complete) == false) {
1357 bus->cmd_err = -EIO;
1358 complete(&bus->cmd_complete);
1360 bus->own_slave_addr = 0xFF;
1361 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1367 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1369 bus->stop_ind = I2C_SLAVE_DONE_IND;
1371 if (bus->operation == I2C_READ_OPER)
1372 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1375 npcm_i2c_slave_send_rd_buf(bus);
1378 bus->stop_ind = I2C_NO_STATUS_IND;
1385 bus->operation = I2C_NO_OPER;
1386 bus->own_slave_addr = 0xFF;
1387 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1388 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1389 if (bus->fifo_use) {
1390 npcm_i2c_clear_fifo_int(bus);
1391 npcm_i2c_clear_rx_fifo(bus);
1392 npcm_i2c_clear_tx_fifo(bus);
1395 bus->reg + NPCM_I2CFIF_CTS);
1397 bus->state = I2C_IDLE;
1402 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1403 ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1404 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1405 bus->master_or_slave = I2C_SLAVE;
1406 if (bus->operation == I2C_READ_OPER)
1407 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1408 bus->operation = I2C_WRITE_OPER;
1409 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1412 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1413 npcm_i2c_slave_rd_wr(bus);
1422 bus->master_or_slave = I2C_SLAVE;
1423 npcm_i2c_clear_fifo_int(bus);
1424 npcm_i2c_clear_rx_fifo(bus);
1425 npcm_i2c_clear_tx_fifo(bus);
1426 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1427 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1429 bus->operation = I2C_WRITE_OPER;
1431 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1433 bus->operation = I2C_READ_OPER;
1435 if (bus->own_slave_addr == 0xFF) {
1437 val = ioread8(bus->reg + NPCM_I2CCST);
1444 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1445 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1456 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1458 bus->own_slave_addr = addr;
1459 if (bus->PEC_mask & BIT(info))
1460 bus->PEC_use = true;
1462 bus->PEC_use = false;
1465 bus->own_slave_addr = 0;
1467 bus->own_slave_addr = 0x61;
1478 if ((bus->state == I2C_OPER_STARTED &&
1479 bus->operation == I2C_READ_OPER &&
1480 bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1481 bus->stop_ind == I2C_SLAVE_RCV_IND) {
1483 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1488 bus->stop_ind = I2C_SLAVE_XMIT_IND;
1490 bus->stop_ind = I2C_SLAVE_RCV_IND;
1491 bus->state = I2C_SLAVE_MATCH;
1492 npcm_i2c_slave_rd_wr(bus);
1493 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1499 (bus->fifo_use &&
1500 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1501 npcm_i2c_slave_rd_wr(bus);
1502 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1511 npcm_i2c_eob_int(bus, false);
1512 npcm_i2c_clear_master_status(bus);
1521 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1523 bus->slave = client;
1528 spin_lock_irqsave(&bus->lock, lock_flags);
1530 npcm_i2c_init_params(bus);
1531 bus->slv_rd_size = 0;
1532 bus->slv_wr_size = 0;
1533 bus->slv_rd_ind = 0;
1534 bus->slv_wr_ind = 0;
1536 bus->PEC_use = true;
1538 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1539 client->addr, bus->PEC_use);
1541 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1542 npcm_i2c_clear_fifo_int(bus);
1543 npcm_i2c_clear_rx_fifo(bus);
1544 npcm_i2c_clear_tx_fifo(bus);
1545 npcm_i2c_slave_int_enable(bus, true);
1547 spin_unlock_irqrestore(&bus->lock, lock_flags);
1553 struct npcm_i2c *bus = client->adapter->algo_data;
1556 spin_lock_irqsave(&bus->lock, lock_flags);
1557 if (!bus->slave) {
1558 spin_unlock_irqrestore(&bus->lock, lock_flags);
1561 npcm_i2c_slave_int_enable(bus, false);
1562 npcm_i2c_remove_slave_addr(bus, client->addr);
1563 bus->slave = NULL;
1564 spin_unlock_irqrestore(&bus->lock, lock_flags);
1569 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1575 fifo_bytes = npcm_i2c_fifo_usage(bus);
1576 rcount = bus->rd_size - bus->rd_ind;
1585 if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1586 fifo_bytes = rcount - bus->data->fifo_size;
1590 bus->state = I2C_STOP_PENDING;
1591 bus->stop_ind = ind;
1592 npcm_i2c_eob_int(bus, true);
1594 npcm_i2c_master_stop(bus);
1595 npcm_i2c_read_fifo(bus, fifo_bytes);
1597 npcm_i2c_read_fifo(bus, fifo_bytes);
1598 rcount = bus->rd_size - bus->rd_ind;
1599 npcm_i2c_set_fifo(bus, rcount, -1);
1603 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1607 if (bus->fifo_use)
1608 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1611 if (bus->wr_ind == bus->wr_size) {
1612 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1622 if (bus->rd_size == 0) {
1624 npcm_i2c_eob_int(bus, true);
1625 bus->state = I2C_STOP_PENDING;
1626 bus->stop_ind = I2C_MASTER_DONE_IND;
1627 npcm_i2c_master_stop(bus);
1629 npcm_i2c_wr_byte(bus, 0xFF);
1633 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1635 npcm_i2c_master_start(bus);
1643 if (bus->rd_size == 1)
1644 npcm_i2c_stall_after_start(bus, true);
1647 bus->operation = I2C_READ_OPER;
1649 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1653 if (!bus->fifo_use || bus->wr_size == 1) {
1654 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1656 wcount = bus->wr_size - bus->wr_ind;
1657 npcm_i2c_set_fifo(bus, -1, wcount);
1659 npcm_i2c_write_to_fifo_master(bus, wcount);
1664 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1670 block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1676 if (bus->rd_ind == 0) { /* first byte handling: */
1677 if (bus->read_block_use) {
1679 data = npcm_i2c_rd_byte(bus);
1681 bus->rd_size = data + block_extra_bytes_size;
1682 bus->rd_buf[bus->rd_ind++] = data;
1685 if (bus->fifo_use) {
1686 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1688 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1691 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1692 npcm_i2c_stall_after_start(bus, false);
1694 npcm_i2c_clear_tx_fifo(bus);
1695 npcm_i2c_master_fifo_read(bus);
1698 if (bus->rd_size == block_extra_bytes_size &&
1699 bus->read_block_use) {
1700 bus->state = I2C_STOP_PENDING;
1701 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1702 bus->cmd_err = -EIO;
1703 npcm_i2c_eob_int(bus, true);
1704 npcm_i2c_master_stop(bus);
1705 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1707 npcm_i2c_master_fifo_read(bus);
1712 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1714 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1715 npcm_i2c_nack(bus);
1716 bus->stop_ind = I2C_BUS_ERR_IND;
1717 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1721 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1725 if (bus->nack_cnt < ULLONG_MAX)
1726 bus->nack_cnt++;
1728 if (bus->fifo_use) {
1733 if (bus->operation == I2C_WRITE_OPER)
1734 bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1737 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1741 bus->stop_ind = I2C_NACK_IND;
1743 if (npcm_i2c_is_master(bus)) {
1745 npcm_i2c_eob_int(bus, false);
1746 npcm_i2c_master_stop(bus);
1749 npcm_i2c_rd_byte(bus);
1752 * The bus is released from stall only after the SW clears
1755 npcm_i2c_clear_master_status(bus);
1756 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1758 /* Verify no status bits are still set after bus is released */
1759 npcm_i2c_clear_master_status(bus);
1761 bus->state = I2C_IDLE;
1765 * In such case, the bus is released from stall only after the
1768 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1772 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1774 if (bus->ber_cnt < ULLONG_MAX)
1775 bus->ber_cnt++;
1776 bus->stop_ind = I2C_BUS_ERR_IND;
1777 if (npcm_i2c_is_master(bus)) {
1778 npcm_i2c_master_abort(bus);
1780 bus->ber_state = true;
1781 npcm_i2c_clear_master_status(bus);
1784 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1786 bus->cmd_err = -EAGAIN;
1787 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1789 bus->state = I2C_IDLE;
1793 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1795 npcm_i2c_eob_int(bus, false);
1796 bus->state = I2C_IDLE;
1797 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1801 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1803 if (npcm_i2c_is_quick(bus)) {
1804 bus->state = I2C_STOP_PENDING;
1805 bus->stop_ind = I2C_MASTER_DONE_IND;
1806 npcm_i2c_eob_int(bus, true);
1807 npcm_i2c_master_stop(bus);
1808 } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1813 npcm_i2c_nack(bus);
1817 npcm_i2c_stall_after_start(bus, false);
1820 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1824 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1828 if (!npcm_i2c_is_master(bus))
1831 if (bus->state == I2C_IDLE) {
1832 bus->stop_ind = I2C_WAKE_UP_IND;
1834 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1839 npcm_i2c_stall_after_start(bus, true);
1841 npcm_i2c_stall_after_start(bus, false);
1849 if (bus->wr_size == 0 && bus->rd_size == 1)
1850 npcm_i2c_stall_after_start(bus, true);
1855 npcm_i2c_select_bank(bus, I2C_BANK_1);
1857 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1862 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1866 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1875 if (bus->wr_size)
1876 npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1878 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1880 bus->state = I2C_OPER_STARTED;
1882 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1883 npcm_i2c_wr_byte(bus, bus->dest_addr);
1885 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1888 if (bus->operation == I2C_WRITE_OPER)
1889 npcm_i2c_irq_master_handler_write(bus);
1890 else if (bus->operation == I2C_READ_OPER)
1891 npcm_i2c_irq_master_handler_read(bus);
1895 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1900 i2cst = ioread8(bus->reg + NPCM_I2CST);
1903 npcm_i2c_irq_handle_nmatch(bus);
1908 npcm_i2c_irq_handle_nack(bus);
1914 npcm_i2c_irq_handle_ber(bus);
1920 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1922 ioread8(bus->reg + NPCM_I2CCST3)))) {
1923 npcm_i2c_irq_handle_eob(bus);
1926 if (bus->slave)
1927 iowrite8(bus->slave->addr | NPCM_I2CADDR_SAEN,
1928 bus->reg + NPCM_I2CADDR1);
1935 npcm_i2c_irq_handle_stall_after_start(bus);
1941 (bus->fifo_use &&
1942 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1943 npcm_i2c_irq_handle_sda(bus, i2cst);
1957 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1962 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1963 bus->num, bus->dest_addr);
1964 npcm_i2c_reset(bus);
1965 bus->ber_state = false;
1969 npcm_i2c_int_enable(bus, false);
1970 npcm_i2c_disable(bus);
1971 npcm_i2c_enable(bus);
1972 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1973 npcm_i2c_clear_tx_fifo(bus);
1974 npcm_i2c_clear_rx_fifo(bus);
1975 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1976 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1977 npcm_i2c_stall_after_start(bus, false);
1980 npcm_i2c_select_bank(bus, I2C_BANK_1);
1983 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1986 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1987 npcm_i2c_set_fifo(bus, -1, 0);
1992 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
2004 npcm_i2c_wr_byte(bus, bus->dest_addr);
2005 npcm_i2c_master_start(bus);
2010 if (npcm_i2c_is_master(bus) > 0) {
2012 npcm_i2c_master_stop(bus);
2016 npcm_i2c_reset(bus);
2017 npcm_i2c_int_enable(bus, true);
2024 if (bus->rec_fail_cnt < ULLONG_MAX)
2025 bus->rec_fail_cnt++;
2027 if (bus->rec_succ_cnt < ULLONG_MAX)
2028 bus->rec_succ_cnt++;
2030 bus->ber_state = false;
2037 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
2038 struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
2061 * and bus frequency.
2062 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
2063 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
2067 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
2073 bus->bus_freq = bus_freq_hz;
2095 if (bus->apb_clk >= smb_timing[scl_table_cnt].core_clk)
2103 bus->reg + NPCM_I2CCTL2);
2108 bus->reg + NPCM_I2CCTL3);
2111 npcm_i2c_select_bank(bus, I2C_BANK_0);
2119 iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT);
2120 iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT);
2122 iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5);
2125 iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4);
2128 npcm_i2c_select_bank(bus, I2C_BANK_1);
2133 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
2140 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
2144 npcm_i2c_int_enable(bus, false);
2145 npcm_i2c_disable(bus);
2148 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
2149 bus->fifo_use = true;
2150 npcm_i2c_select_bank(bus, I2C_BANK_0);
2151 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
2153 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
2154 npcm_i2c_select_bank(bus, I2C_BANK_1);
2156 bus->fifo_use = false;
2160 ret = npcm_i2c_init_clk(bus, bus_freq_hz);
2162 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
2167 npcm_i2c_enable(bus);
2168 bus->state = I2C_IDLE;
2169 val = ioread8(bus->reg + NPCM_I2CCTL1);
2171 iowrite8(val, bus->reg + NPCM_I2CCTL1);
2173 npcm_i2c_reset(bus);
2176 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
2177 dev_warn(bus->dev, " I2C%d SDA=%d SCL=%d, attempting to recover\n", bus->num,
2178 npcm_i2c_get_SDA(&bus->adap), npcm_i2c_get_SCL(&bus->adap));
2179 if (npcm_i2c_recovery_tgclk(&bus->adap)) {
2180 dev_err(bus->dev, "I2C%d init fail: SDA=%d SCL=%d\n",
2181 bus->num, npcm_i2c_get_SDA(&bus->adap),
2182 npcm_i2c_get_SCL(&bus->adap));
2187 npcm_i2c_int_enable(bus, true);
2191 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
2197 bus->state = I2C_DISABLE;
2198 bus->master_or_slave = I2C_SLAVE;
2199 bus->int_time_stamp = 0;
2201 bus->slave = NULL;
2211 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2222 struct npcm_i2c *bus = dev_id;
2224 if (npcm_i2c_is_master(bus))
2225 bus->master_or_slave = I2C_MASTER;
2227 if (bus->master_or_slave == I2C_MASTER) {
2228 bus->int_time_stamp = jiffies;
2229 if (!npcm_i2c_int_master_handler(bus))
2233 if (bus->slave) {
2234 bus->master_or_slave = I2C_SLAVE;
2235 if (npcm_i2c_int_slave_handler(bus))
2240 npcm_i2c_clear_master_status(bus);
2245 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2250 if (bus->state != I2C_IDLE) {
2251 bus->cmd_err = -EBUSY;
2254 bus->wr_buf = write_data;
2255 bus->wr_size = nwrite;
2256 bus->wr_ind = 0;
2257 bus->rd_buf = read_data;
2258 bus->rd_size = nread;
2259 bus->rd_ind = 0;
2260 bus->PEC_use = 0;
2264 bus->PEC_use = use_PEC;
2266 bus->read_block_use = use_read_block;
2268 bus->operation = I2C_READ_OPER;
2270 bus->operation = I2C_WRITE_OPER;
2271 if (bus->fifo_use) {
2274 npcm_i2c_select_bank(bus, I2C_BANK_1);
2276 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2279 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2282 bus->state = I2C_IDLE;
2283 npcm_i2c_stall_after_start(bus, true);
2284 npcm_i2c_master_start(bus);
2291 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2302 if (bus->state == I2C_DISABLE) {
2303 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2341 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2345 time_left = jiffies + bus->adap.timeout / bus->adap.retries + 1;
2348 * we must clear slave address immediately when the bus is not
2352 spin_lock_irqsave(&bus->lock, flags);
2353 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2355 if (!bus_busy && bus->slave)
2356 iowrite8((bus->slave->addr & 0x7F),
2357 bus->reg + NPCM_I2CADDR1);
2359 spin_unlock_irqrestore(&bus->lock, flags);
2368 * from the bus->dest_addr for the i2c_recover_bus() call later.
2371 * the i2c bus if some error condition occurs.
2376 bus->dest_addr = i2c_8bit_addr_from_msg(msg0) & ~I2C_M_RD;
2379 * Check the BER (bus error) state, when ber_state is true, it means that the module
2380 * detects the bus error which is caused by some factor like that the electricity
2381 * noise occurs on the bus. Under this condition, the module is reset and the bus
2384 * While ber_state is false, the module reset and bus recovery also get done as the
2385 * bus is busy.
2387 if (bus_busy || bus->ber_state) {
2388 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2389 npcm_i2c_reset(bus);
2394 npcm_i2c_init_params(bus);
2395 bus->msgs = msgs;
2396 bus->msgs_num = num;
2397 bus->cmd_err = 0;
2398 bus->read_block_use = read_block;
2400 reinit_completion(&bus->cmd_complete);
2402 npcm_i2c_int_enable(bus, true);
2404 if (npcm_i2c_master_start_xmit(bus, nwrite, nread,
2412 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2413 timeout = max_t(unsigned long, bus->adap.timeout / bus->adap.retries,
2415 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2419 if (bus->timeout_cnt < ULLONG_MAX)
2420 bus->timeout_cnt++;
2421 if (bus->master_or_slave == I2C_MASTER) {
2423 bus->cmd_err = -EIO;
2424 bus->state = I2C_IDLE;
2429 /* if there was BER, check if need to recover the bus: */
2430 if (bus->cmd_err == -EAGAIN)
2431 bus->cmd_err = i2c_recover_bus(adap);
2438 else if (bus->cmd_err &&
2439 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2440 npcm_i2c_reset(bus);
2443 npcm_i2c_stall_after_start(bus, false);
2444 npcm_i2c_eob_int(bus, false);
2448 if (bus->slave)
2449 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2450 bus->reg + NPCM_I2CADDR1);
2452 npcm_i2c_int_enable(bus, false);
2454 return bus->cmd_err;
2482 struct npcm_i2c *bus)
2484 debugfs_create_u64("ber_cnt", 0444, bus->adap.debugfs, &bus->ber_cnt);
2485 debugfs_create_u64("nack_cnt", 0444, bus->adap.debugfs, &bus->nack_cnt);
2486 debugfs_create_u64("rec_succ_cnt", 0444, bus->adap.debugfs, &bus->rec_succ_cnt);
2487 debugfs_create_u64("rec_fail_cnt", 0444, bus->adap.debugfs, &bus->rec_fail_cnt);
2488 debugfs_create_u64("timeout_cnt", 0444, bus->adap.debugfs, &bus->timeout_cnt);
2489 debugfs_create_u64("tx_complete_cnt", 0444, bus->adap.debugfs, &bus->tx_complete_cnt);
2498 struct npcm_i2c *bus;
2503 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2504 if (!bus)
2507 bus->dev = &pdev->dev;
2509 bus->data = of_device_get_match_data(dev);
2510 if (!bus->data) {
2515 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2520 bus->apb_clk = clk_get_rate(i2c_clk);
2528 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2530 bus->reg = devm_platform_ioremap_resource(pdev, 0);
2531 if (IS_ERR(bus->reg))
2532 return PTR_ERR(bus->reg);
2534 spin_lock_init(&bus->lock);
2535 init_completion(&bus->cmd_complete);
2537 adap = &bus->adap;
2541 * The users want to connect a lot of masters on the same bus.
2542 * This timeout is used to determine the time it takes to take bus ownership.
2548 adap->algo_data = bus;
2562 npcm_i2c_int_enable(bus, false);
2564 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2565 dev_name(bus->dev), bus);
2569 ret = __npcm_i2c_init(bus, pdev);
2575 i2c_set_adapdata(adap, bus);
2577 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2578 bus->num);
2579 ret = i2c_add_numbered_adapter(&bus->adap);
2583 platform_set_drvdata(pdev, bus);
2584 npcm_i2c_init_debugfs(pdev, bus);
2591 struct npcm_i2c *bus = platform_get_drvdata(pdev);
2593 spin_lock_irqsave(&bus->lock, lock_flags);
2594 npcm_i2c_disable(bus);
2595 spin_unlock_irqrestore(&bus->lock, lock_flags);
2596 i2c_del_adapter(&bus->adap);