Lines Matching +full:600 +full:ns

263 	 * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns
264 	 * fast mode, min LOW and HIGH period are 1300 ns and 600 ns
271 		cnt_high = (cnt_period * 600) / (1300 + 600);
303 	 * a i2c device must internally provide a hold time at least 300ns
305 	 *	Standard Mode: min=300ns, max=3450ns
306 	 *	Fast Mode: min=0ns, max=900ns
308 	 *	Standard Mode: min=250ns, max=infinite
309 	 *	Fast Mode: min=100(250ns is recommended), max=infinite
312 	 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
313 	 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns